2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD) 2020
DOI: 10.1109/ispsd46842.2020.9170181
|View full text |Cite
|
Sign up to set email alerts
|

Modular Multilevel SOI-CMOS Active Gate Driver Architecture for SiC MOSFETs

Abstract: High Voltage SiC power MOSFETs have specific driving challenges such as a reduced short circuit capability (compared to Si IGBTs) and a weak field oxide layer, a large gate to source driving voltage (compared to GaN FETs), a high electric field under negative gate bias in off-state and a high switching speed. The negative bias in off-state creates a high stress which reduces the reliability of the SiC MOSFET. The high positive gate bias can generate large drain saturation current in case of short circuit event… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1

Citation Types

0
3
0

Year Published

2021
2021
2024
2024

Publication Types

Select...
4
4

Relationship

0
8

Authors

Journals

citations
Cited by 12 publications
(3 citation statements)
references
References 14 publications
0
3
0
Order By: Relevance
“…A state-of-the-art architecture of an active gate driver for SiC MOSFET was designed by Nicholas et al 136 The design is a modular multilevel active gate driver that provides new perceptions to control the level of voltage of the SiC-MOSFETs during their switching modes. The major advantages of the architecture are to reduce the stress of detection of short-circuit and protection of the device using basic low differential voltage sub-modules, and to reduce the electric field of the gate stack on SiC, during on-state while protecting the Miller coupling.…”
Section: Architecture Of Gate Oxides On Sicmentioning
confidence: 99%
“…A state-of-the-art architecture of an active gate driver for SiC MOSFET was designed by Nicholas et al 136 The design is a modular multilevel active gate driver that provides new perceptions to control the level of voltage of the SiC-MOSFETs during their switching modes. The major advantages of the architecture are to reduce the stress of detection of short-circuit and protection of the device using basic low differential voltage sub-modules, and to reduce the electric field of the gate stack on SiC, during on-state while protecting the Miller coupling.…”
Section: Architecture Of Gate Oxides On Sicmentioning
confidence: 99%
“…The digital units implementing the logic processing are supplied by low voltage to reduce power dissipation, while the circuits composing the output stage are powered by high voltage to carry enough energy for loads. For communication between circuits supplied with different voltage, the level shifter becomes a critical interface in the gate driver [11,12]. In the medium/high-voltage gate driver or half-bridge gate driver, FHV-LS can transfer the control signal from low-side power rail to high-side power rail with floating-ground, sending commands to the output of gate driver.…”
Section: Introductionmentioning
confidence: 99%
“…Over the past few decades, several approaches to quick and lossless gate-driving of MOSFET switches have been introduced [10]- [15]. Common state-of-the-art approaches include charge-pump [10] and bootstrap [11], [12] solutions. To reduce losses, [13] suggested saving the energy stored in the input capacitance of the MOSFET in an external resonant circuit.…”
mentioning
confidence: 99%