CMOS Analog Design Using All-Region MOSFET Modeling

Abstract

Covering the essentials of analog circuit design, this book takes a unique design approach based on a MOSFET model valid for all operating regions, rather than the standard square-law model. Opening chapters focus on device modeling, integrated circuit technology, and layout, whilst later chapters go on to cover noise and mismatch, and analysis and design of the basic building blocks of analog circuits, such as current mirrors, voltage references, voltage amplifiers, and operational amplifiers. An introduction to continuous-time filters is also provided, as are the basic principles of sampled-data circuits, especially switched-capacitor circuits. The final chapter then reviews MOSFET models and describes techniques to extract design parameters. With numerous design examples and exercises also included, this is ideal for students taking analog CMOS design courses and also for circuit designers who need to shorten the design cycle.

Channel length influence on the analog characteristics of asymmetric self-cascode association of SOI transistors

“…It is also possible to note that in any combination of Lj and L2, the use of A-se is able to increase the breakdown voltage (BVu,) to values above 4V, while in the S-SC, BVns remains below 2.5V. On the other hand, the saturation voltage, which is already larger in S-SC in comparison to individual transistors [2], further increases when M 2 with low VT is used. An increased IDs level can be observed in A-SC when compared to S-SC, due to the larger M 2 resistance for transistors with higher V T values.…”

“…These advantages are related to the reduced junction capacitance due to the presence of buried oxide underneath the active silicon region, reduced body factor (n) and larger transconductance. However, some degradation on the analog perfonnance of FD SOl transistors may be expected due to the high electric field near the drain that increases the output conductance due to channel length modulation [2] and may lead to the occurrence of parasitic bipolar effects, due to impact ionization carriers generation, reducing the breakdown voltage [3]. Additionally, the continuous devices' downscaling contributes to the degradation of output conductance and breakdown voltage, imposing limits to the applied voltage bias range.…”

“…The simplest way to improve the output conductance in MOS transistors is to increase its channel length [4]. However, apart from increasing area consumption and saturation voltage, it may degrade other analog properties, such as the cutoff frequency, which is inversely proportional to the square of channel lenglh [2].…”

Spike-Time-Dependent Encoding for Neuromorphic Processors

“…However, digital implementations usually require more transistors than their analog equivalents. This in turn necessitates larger die sizes which consume more power in most cases [Dautriche 2011;Joubert et al 2012;Sarpeshkar 1998;Schneider and Galup-Montoro 2010].…”

Analogue CMOS prototype vision chip with prewitt edge processing

“…At t 2 SHT is also turned off and (n1) is isolated, keeping almost constant its instant voltage V(t 2 ) n1 . Figure 6 shows V n1 versus time graph for the current design; the maximum V n1 voltage swing is 1.5 V. MP1 and MP2 produce voltage disturbances when they are turned off due to channel charge injection [12]. To reduce this problem, channel length and width from MP1 and MP2 are minimum dimensions (S = W/L = 0.6 l/0.4 l for CMOS TSMC 35 lm; this technology is being used in the current design), having few channel charge to redistribute.…”