CMOS cascode LNA with post-distortion cancellation linearizer for wireless communications

El-Khatib, Ziad; Tlili, Boutheina; Amer, Muhieddin; Fuller, Lynn

doi:10.1109/icecta.2017.8252022

Cited by 3 publications

(1 citation statement)

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“…However, the common problem existing in all the reported DS methods is its difficulty with achieving good input matching and optimized noise performance. Post-distortion usually achieves stable distortion rejection and high linearity with an auxiliary saturated transistor, while the auxiliary transistors consume extra power to operate in saturation mode [10,11]. Several post-distortion (PD) networks have been proposed to enhance the linearity of LNA [10,12,13].…”

Section: Introductionmentioning

confidence: 99%

A Triple-Cascode X-Band LNA Design with Modified Post-Distortion Network

Cao

et al. 2021

Electronics

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This work proposes a novel linearized low noise amplifier (LNA) for X-band applications with flat power gain, low noise performance and enhanced linearity. In this study, a triple-cascode topology with dual-resonant network is utilized and a modified post-distortion network is introduced to improve the linearity. The LNA utilizes a subthreshold auxiliary NMOS transistor to reduce the nonlinearity with low power consumption. In addition, a methodology is proposed to predict the characteristic of the linearity performance of the proposed LNA with modified post-distortion network. With a small increase of 1 mW in power consumption due to the inclusion of the post-distortion network, the input intercept point IIP3 is improved and lies in the range of −3 to +8 dBm over the frequency range from 8 to 12 GHz. Implemented in Global Foundries 130 nm CMOS process, the LNA achieves a peak gain of 18 dB, and a 1.3 dB minimum NF over 8 to 12 GHz. The proposed LNA requires an area of 1.2 mm2 and a power of 18 mW.

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