CMOS current-controlled oscillators using multiple-feedback-loop ring architectures

Jeong, Dong-Youl; Chai, Sang-Hoon; Song, Wonchul; Cho, Gyu‐Hyeong

doi:10.1109/isscc.1997.585452

Cited by 27 publications

(3 citation statements)

References 3 publications

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“…Utilizing feedforward paths such as: multiplefeedback loops, dual-delay paths, and multiple-pass loop have been investigated in several papers [5][6][7][8][9]. Although they have very wide tuning range, they suffer from very high power dissipation.…”

Section: Rvcos and Low -Voltage Techniquesmentioning

confidence: 99%

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A low-voltage voltage-controlled ring-oscillator employing dynamic-threshold-MOS and body-biasing techniques

Abdollahvand

Oliveira

Gomes

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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In this paper a four-stage self-biased voltagecontrolled oscillator (VCO) is presented. The proposed ringoscillator circuit employs a combination of dynamic-threshold-MOS (DT-MOS) and bulk-driven transistors to design lowvoltage low-power VCO with high oscillation frequency. By using an auxiliary body-driven latch, the VCO achieves a wide operating frequency range from 0.88 to 1.36 GHz (more than 40% tuning range). Simulation results in a 65-nm CMOS technology shows frequency variations of 3% against temperature variation of -20 ºC to 85 ºC, with only 0.36 mW power consumption using a 0.7 V supply voltage.

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Section: Rvcos and Low -Voltage Techniquesmentioning

confidence: 99%

“…Although they have very wide tuning range, they suffer from very high power dissipation. The reported power dissipation for [5] and [6] are 78mW and 30mW respectively (the power consumption of the presented VCO in [7] is not mentioned). The [8,9] tried to reduce the power consumption of the multi-loop structure.…”

Section: Rvcos and Low -Voltage Techniquesmentioning

confidence: 99%

A low-voltage voltage-controlled ring-oscillator employing dynamic-threshold-MOS and body-biasing techniques

Abdollahvand

Oliveira

Gomes

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…LOCs1 is the first step towards optical links for the readout upgrade of the ATLAS LAr calorimeter for the super LHC. The serializer consists of a serializing unit, a phase lock loop (PLL) clock generator and a current-mode-logic (CML) driver as shown [7,9,10] is used to boost the operating frequency of voltage control oscillator (VCO). The PLL loop bandwidth is programmable for adapting different reference clock qualities.…”

Section: The Designmentioning

confidence: 99%

Update on the high speed serializer ASIC development for ATLAS Liquid Argon calorimeter upgrade

Liu

2011

J. Inst.

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We have been developing a serializer application-specific integrated circuit (ASIC) based on a commercial 0.25-μm silicon-on-sapphire (SOS) CMOS technology for the ATLAS liquid argon calorimeter front-end electronics upgrade. The first prototype, a 5 Gbps 16:1 serializer has been designed, fabricated, and tested in lab environment and in a 200 MeV proton beam. The test results indicate that the first prototype meets the design goals. The second prototype, a double-lane, 8 Gbps per lane serializer is under development. The post-layout simulation indicates that 8 Gbps is achievable. In this paper we present the design and the test results of the first prototype and the design and status of the second prototype. KEYWORDS: VLSI circuits; Analogue electronic circuits; Front-end electronics for detector readout. 2.1 The design 1 2.2 The lab test 2 2.3 The radiation test 3 2.4 The LCPLL 4 3. The design and test of a single-lane serializer 5 3.1 The design of the double-lane serializer 1 3.2 The design of the laser driver array 2 4. Conclusion 5

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Area‐efficient ultra‐wide‐tuning‐range ring oscillators in 65‐nm complementary metal–oxide–semiconductor

Yang,

Chen,

Cheng

et al. 2024

Circuit Theory & Apps

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In this paper, to analyze the tuning range (TR) of transistors, we introduced two streamlined modeling approaches that can precisely predict the extent and direction of the TR. The first approach, known as the average DC (Id) method, employed a simplified circuit model to dissect transistor characteristics, enabling us to understand the general trajectory of the TR. The second approach involved the transient current Id (tc) method, which offers a nuanced portrayal of the transistor's real‐world performance. By analyzing the current fluctuations within the transistor during transient states, its tuning capabilities could be more accurately ascertained. Further, this paper presents several designs for ultra‐wide‐tuning‐range complementary metal–oxide–semiconductor (CMOS) voltage‐controlled oscillators (VCOs) that employ a novel two‐mode current‐starved delay cell, featuring a tunable transistor‐based current source for coarse frequency adjustment operating in synergy with a varactor for precise tuning. Using the 65‐nm CMOS process, three prototype VCOs (Designs 2/3/4) based on the new cell and targeting different numbers of phases and performance were fabricated, thoroughly characterized, and compared with their traditional inverter‐based counterpart (Design 1). Design 1 featured an inverter‐based four‐phase structure, with an output frequency range of 3.14–9.82 GHz, i.e., a radio frequency (RF) TR of 103%, with phase noise (PN) ranging from 137.7 to 132.1 dBc/Hz at an offset of 100 MHz, figure of merit with tuning range and area (FoMTA) varying from 200.7 to 205.1 dBc/Hz, and area of 0.0036 mm2. In contrast, Designs 2/3/4, based on the new delay cell, featured 8/3/4 phases, with output frequencies in the ranges of 1.14–9.17, 1.26–16.53, and 1.15–18.32 GHz, respectively, resulting in increased RF TRs of 155.8%, 171.7% and 176.4%, as well as PN at an offset of 100 MHz in the ranges of 142.1–138, 130.5–131.3, and 131.9–129.6 dBc/Hz, respectively. This yielded better FoMTAs in the ranges of 201.2–209.9, 205.3–217.9, and 194.1–209.9 dBc/Hz, thus allowing the VCOs to maintain consistent performance across the frequency band and occupy comparable or smaller silicon areas of 0.00425, 0.000972, and 0.00348 mm2 in the same 65 nm technology. These designs showcase the versatility and efficiency of the two‐mode current‐starved delay architecture, which offers wide TRs, tiny areas, and competitive performance metrics for various applications in RF integrated circuits.

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CMOS current-controlled oscillators using multiple-feedback-loop ring architectures

Cited by 27 publications

References 3 publications

A low-voltage voltage-controlled ring-oscillator employing dynamic-threshold-MOS and body-biasing techniques

A low-voltage voltage-controlled ring-oscillator employing dynamic-threshold-MOS and body-biasing techniques

Update on the high speed serializer ASIC development for ATLAS Liquid Argon calorimeter upgrade

Area‐efficient ultra‐wide‐tuning‐range ring oscillators in 65‐nm complementary metal–oxide–semiconductor

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