2014
DOI: 10.2298/fuee1402251c
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CMOS IC radiation hardening by design

Abstract: Design techniques for radiation hardening of integrated circuits in commercial CMOS technologies are presented. Circuits designed with the proposed approaches are more tolerant to both total dose and to single event effects. The main drawback of the techniques for radiation hardening by design is the increase of silicon area, compared with a conventional design.

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Cited by 11 publications
(10 citation statements)
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“…The application of Buck in space has to consider all kinds of radiation effect. For CMOS devices, total ionizing dose (TID) effect is prone to occur in the radiation environment, and it will lead to threshold voltage shift [1,2], transconductance degradation [3,4], carrier mobility reduction and leakage current [5,6,7,8], resulting in the degradation or failure of devices and circuits [9,10,11,12,13,14,15]. In this aspect, it is of great significance to research on the radiation-resistant reinforcement of Buck.…”
Section: Introductionmentioning
confidence: 99%
“…The application of Buck in space has to consider all kinds of radiation effect. For CMOS devices, total ionizing dose (TID) effect is prone to occur in the radiation environment, and it will lead to threshold voltage shift [1,2], transconductance degradation [3,4], carrier mobility reduction and leakage current [5,6,7,8], resulting in the degradation or failure of devices and circuits [9,10,11,12,13,14,15]. In this aspect, it is of great significance to research on the radiation-resistant reinforcement of Buck.…”
Section: Introductionmentioning
confidence: 99%
“…Traditionally, the radiation tolerance for PROM is achieved by using specific manufacturing process, known as "Radiation Hardening by Processes" (RHBP), which has a drawback by entailing high costs. To address this issue, Radiation Hardened By Design (RHBD) techniques have been proposed [4]. The RHBD uses layout and circuit design techniques for radiation hardness and radiation-tolerant ICs can be fabricated by standard CMOS process.…”
Section: Introductionmentioning
confidence: 99%
“…The circuit variants differ with respect to the topology, the use of cascode stages, the supply voltage and the oxide thickness of the utilized transistors. All topologies were implemented using regular radiation-hardening-bydesign (RHBD) layout techniques, such as extended use of guard rings, substrate contacts, increased transistor sizes for hardening against ASETs, whilst edgeless NMOS devices were employed for hardening against total ionization dose (TID) [9], [55], [56]. The integrated circuits were exposed to heavy ions (Si, Kr and Xe) and the resulting ASETs were recorded at the output of each topology independently by using a high-speed oscilloscope.…”
mentioning
confidence: 99%