CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) Circuit Design for Nanosecond Quantum-Bit Read-out

Gurrieri, Thomas M.; Carroll, M. S.; Lilly, Michael; Levy, James E.

doi:10.1109/nano.2008.183

Cited by 13 publications

(17 citation statements)

References 5 publications

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“…CMOS circuit design to control and readout of an SET device operating at mK temperature is duly getting much research focus in recent years [1], [2]. Established SET readout method such as the radio frequency SET architecture has demonstrated sensitivity better than lOJ-LV/VHZ at megahertz bandwidth [1], but it is not practical for scalable design where numerous SETs can be measured simultaneously.…”

Section: Introductionmentioning

confidence: 99%

“…For such schemes, each sensing SET requires long cable connection from the base temperature « lOOmK) of the dilution refrigerator to the room temperature (300K ) observer circuit and thus the speed is limited by the capaci tance of the connection cable. To this end, [2], [3] proposes the perspective of low-temperature CMOS circuit as the most efficient and complete readout architecture where the readout circuit operates at the close proximity of the qubit and the SET device at very low temperature. [3] presents analysis and simulation results of a 4.2K temperature CMOS readout circuit capable of producing one shot digital output at the event of current conduction through the SET.…”

Section: Introductionmentioning

confidence: 99%

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Low power fast cryogenic CMOS circuit for digital readout of single electron transistor

Das

Lehmann

2011

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)

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We present a cryogenic CMOS circuit with signif icant performance improvements compared to previously pro posed single-shot Single Electron Transistor readout circuit. The new readout architecture developed on commercial O.5J.tm SOl CMOS process is desinged to operate at 4.2K temperature and detect the SET signal current as low as 200pA. In addition to very low signal levels, the design process is complicated due to severe power consumption limitations at low temperature and J.tV level drain-source compliance requirement of the SET. The design addresses the low-temperature CMOS irregularities found in published literature and even under the design restrictions andSET specifications, our circuit shows successful digital detection of a SET event with only'" 520ns delay and consumes as low as 761' W power. In addition to speed improvement over previous design (detection time more than l0J.ts), this design is more robust and tolerant to biasing variations.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Low power fast cryogenic CMOS circuit for digital readout of single electron transistor

Das

Lehmann

2011

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)

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“…[21][22][23] Current comparators have shown promise but their thresholds of sensitivity have been near the limits of the current output of SETs, making them difficult to implement without a preamplification stage. 24,25 Cryogenic preamplification using discrete high-electron-mobility-transistors (HEMTs) has been investigated resulting in sufficient SNR for a particular bandwidth. 26 However, HEMTs may require a relatively high power dissipation, and the typical circuit configuration introduces a fixed load resistance in front of the gate that can limit the circuit bandwidth.…”

mentioning

confidence: 99%

Cryogenic preamplification of a single-electron-transistor using a silicon-germanium heterojunction-bipolar-transistor

Curry

England

Bishop

et al. 2015

Applied Physics Letters

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We examine a silicon-germanium heterojunction bipolar transistor (HBT) for cryogenic pre-amplification of a single electron transistor (SET). The SET current modulates the base current of the HBT directly. The HBT-SET circuit is immersed in liquid helium, and its frequency response from low frequency to several MHz is measured. The current gain and the noise spectrum with the HBT result in a signal-to-noise-ratio (SNR) that is a factor of 10−100 larger than without the HBT at lower frequencies. The transition frequency defined by SNR = 1 has been extended by as much as a factor of 10 compared to without the HBT amplification. The power dissipated by the HBT cryogenic pre-amplifier is approximately 5 nW to 5 μW for the investigated range of operation. The circuit is also operated in a single electron charge read-out configuration in the time-domain as a proof-of-principle demonstration of the amplification approach for single spin read-out. Donor spin qubits have recently received increased interest because of the demonstration of high fidelity coherent control of phosphorus donors using a local electron spin resonance technique. 1,2 This approach is of interest both for quantum information 3-5 as well as representing a new experimental platform to investigate the behavior of single impurities in semiconductors using electron and nuclear magnetic resonance. Single-shot readout 6-8 of the spin polarization is an important component of the measurement. It may be accomplished using a wide-band measurement of the single electron transistor 9 (SET) conductance, which is sensitive to the ionization condition of any nearby donors. 10,11 The technique relies on alignment of the neighboring SET chemical potential between discrete Zeeman energy levels. The donor spinup electron ionizes into the SET, leading to a detectable transient change in the local electrostatic potential, while a SET electron waits to reload into the donor as a spindown. The temporary ionization of the donor changes the conductance of the SET, which is measured as a current pulse corresponding to a spin-up electron or no pulse if the electron was spin-down.Read-out fidelity can be no better than what the signal-to-noise-ratio (SNR) provides for a particular bandwidth, although other factors can introduce errors that degrade the fidelity, such as rapid tunneling events that are faster than the bandwidth of the read-out. The donor read-out technique is performed at cryogenic temperatures less than 4 K, which is typically necessary to observe the spin read-out of the donor state at reasonably low magnetic fields. The SET current is subsequently amplified at room-temperature (RT) using one or several amplification stages, typically including a transconductance amplifier. The line capacitance between the transconductance amplifier and the SET typically sets the limits of performance of the circuit. Increased readout bandwidth can improve fidelity, for example, by detecting faster tunnel events, however, the increased bandwidth reduces SNR. The SNR can be i...

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“…This is still relatively slow compared to qubit gating times and it would be desirable to increase the speed. Solid-state qubits in silicon utilizing CMOS compatible materials opens up the possibility of a simpler measurement architecture where the qubit readout circuitry can be directly integrated on chip.It has been calculated that CMOS electronics could offer qubit readout speeds of nano-seconds, with only several nano-watts of power consumption [7].In this paper we will describe the development of a novel Si qubit architecture with fabrication involving materials that are CMOS compatible. We will address some of the material requirements involved within this architecture in order to operate at 100mK.…”

mentioning

confidence: 99%

“…It has been calculated that CMOS electronics could offer qubit readout speeds of nano-seconds, with only several nano-watts of power consumption [7].…”

mentioning

confidence: 99%

Steps Towards Fabricating Cryogenic CMOS Compatible Single Electron Devices

Eng

Eyck

Tracy

et al. 2008

2008 8th IEEE Conference on Nanotechnology

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We describe the development of a novel silicon quantum bit (qubit) device architecture that involves using materials that are compatible with a Sandia National Laboratories (SNL) 0.35 μm complementary metal oxide semiconductor (CMOS) process intended to operate at 100mK. We describe how the qubit structure can be integrated with CMOS electronics, which is believed to have advantages for critical functions like fast single electron electrometry for readout compared to current approaches using radio frequency techniques. Critical materials properties are reviewed and preliminary characterization of the SNL CMOS devices at 4.2K is presented.Among the many variations of qubits, solid-state approaches are often perceived as appealing because of the existing infrastructure and the demonstration of nano-fabricated devices that are necessary for classical computers. One successful solid-state approach for building a qubit has focused on three dimensional confinement of a single electron spin in a quantum dot.Utilizing electrostatic gates in GaAs heterostrostructures, it has been demonstrated [1] that control of coherent two electron spin states can be achieved in a double quantum dot (DQD). However, one critical challenge to GaAs based structures is the short spin decoherence lifetimes due to the hyperfine interaction with the non-zero nuclear spin of the Ga and As isotopes.Solid-state qubit proposals involving electron spins in silicon are viewed to be more attractive because at cryogenic temperatures they have been shown to have longer decoherence lifetimes (T 2 > 10 ms) [2] due to low spin-orbit interaction and zero total nuclear spin in isotopically enriched 28 Si. Although demonstration of a silicon spin qubit has yet to be achieved, recent progress involving QDs in silicon have shown promising results where single electron electrometry and Pauli-blockaded transport have been demonstrated in ultra thin body silicon-oninsulator substrates [3] and modulation doped Si/SiGe heterostructures [4] [5].Readout within a solid-state qubit formed via double quantum dots is achieved by measuring the charge configuration of the double quantum dot via a capacitively coupled charge sensor (e.g. quantum point contact). The two states of the qubit are the singlet and the (m=0) triplet of the two spin system. Spin information is then inferred by applying a driving voltage to push two electrons into a single quantum dot. There is a significant difference in the exchange energy between the singlet and triplet (singlet is lower) allowing the singlet to form as a double occupied quantum dot but not allowing the triplet to transition to two electron occupation. The singlet state is identified, therefore as the one that has more electron charge in a single quantum dot, sensed capacitvely with the electrometer. High fidelity operation of quantum logic devices requires readout that is faster than the decoherence lifetime of the spin, T 2 . Typically these charge sensors have large inherent impedances (> 26 kΩ) and thus the RC delay is a chal...

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CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) Circuit Design for Nanosecond Quantum-Bit Read-out

Cited by 13 publications

References 5 publications

Low power fast cryogenic CMOS circuit for digital readout of single electron transistor

Low power fast cryogenic CMOS circuit for digital readout of single electron transistor

Cryogenic preamplification of a single-electron-transistor using a silicon-germanium heterojunction-bipolar-transistor

Steps Towards Fabricating Cryogenic CMOS Compatible Single Electron Devices

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