CMOS Pixel-Level ADC with Change Detection

Chi, Y.M.; Mallik, Udayan; Choi, E.; Clapp, Matthew; Gauwenberghs, G.; Etienne‐Cummings, Ralph

doi:10.1109/iscas.2006.1692918

Cited by 5 publications

(6 citation statements)

References 6 publications

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“…The ADCs module consists of N row-parallel 6-bit ADCs. Even though a lot of work, such as reported in [ 18 – 21 ], has been done on pixel level ADCs; we still chose the row parallel (named column parallel in some papers) structure [ 22 ] for analog to digital converting. The ADC we implemented in the chip is based on an algorithmic approach [ 23 ].…”

Section: Architecture and Operations Of The Chipmentioning

confidence: 99%

A 1,000 Frames/s Programmable Vision Chip with Variable Resolution and Row-Pixel-Mixed Parallel Image Processors

Lin

Wang

Zhang

et al. 2009

Sensors

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A programmable vision chip with variable resolution and row-pixel-mixed parallel image processors is presented. The chip consists of a CMOS sensor array, with row-parallel 6-bit Algorithmic ADCs, row-parallel gray-scale image processors, pixel-parallel SIMD Processing Element (PE) array, and instruction controller. The resolution of the image in the chip is variable: high resolution for a focused area and low resolution for general view. It implements gray-scale and binary mathematical morphology algorithms in series to carry out low-level and mid-level image processing and sends out features of the image for various applications. It can perform image processing at over 1,000 frames/s (fps). A prototype chip with 64 × 64 pixels resolution and 6-bit gray-scale image is fabricated in 0.18 μm Standard CMOS process. The area size of chip is 1.5 mm × 3.5 mm. Each pixel size is 9.5 μm × 9.5 μm and each processing element size is 23 μm × 29 μm. The experiment results demonstrate that the chip can perform low-level and mid-level image processing and it can be applied in the real-time vision applications, such as high speed target tracking.

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Section: Architecture and Operations Of The Chipmentioning

confidence: 99%

A 1,000 Frames/s Programmable Vision Chip with Variable Resolution and Row-Pixel-Mixed Parallel Image Processors

Lin

Wang

Zhang

et al. 2009

Sensors

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“…The operation of this imager, which can perform both in-pixel change detection and ADC has been presented at previous conferences [3] [8]. As output, the imager provides a standard analog image intensity output as well as a digital flag indicating the presence and direction of intensity changes.…”

Section: System Description a Image Sensormentioning

confidence: 99%

Video Sensor Node for Low-Power Ad-hoc Wireless Networks

Chi

Etienne‐Cummings

Cauwenberghs

et al. 2007

2007 41st Annual Conference on Information Sciences and Systems

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Abstract-A video sensor platform consisting of a smart image sensor with focal plane motion processing is presented. The camera node is intended for ultra-low bandwidth ad-hoc wireless networks with data rates of less than 2kB/sec. To meet the targets of low power consumption and low complexity, the CMOS image sensor (consuming 4.2mW of power at 30fps) autonomously monitors for scene changes, outputting full image data only when relevant. For this sensor node, several different operating configurations leveraging the analog processing and storage capability of the imager, including a full motion DCT based video compression algorithm are shown. The entire sensor module can operate from 3 AA batteries and consumes 225mW at full operation.

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“…As integrated circuits (IC) keep scaling down following Moore's Law, recent trends show a significant number of papers discussing the design of digital pixels [5]- [8] This trend is mainly motivated by the advantages of pixel-level analog-to-digital (A/D) converter such as high SNR, lower power consumption, and very low conversion speeds. Nevertheless, the resulting implementations of in-pixel analog-to-digital converter (ADC) are rather area consuming, strongly restricting the image processing capability of CMOS sensors.…”

Section: Introductionmentioning

confidence: 99%

Design and Implemention of ADC Implanted in 10 000Frame/s High-Speed CMOS Sensor

Wibowo¹,

Affandi²,

Soerowirdjo³

et al. 2012

IJCEE

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Abstract-This paper describes the design of pipeline ADC embedded in a high speed CMOS sensor that has been designed and fabricated by Paindavoine. The idea of ADC to be embedded in the high speed cmos sensor in order to reduce power, integrated so that the output of the CMOS sensor is already in digital form. An ADC is designed using Pipeline topology with considerations is simple in the design because it just makes a stage and the next stage is duplicated, relatively high speed and have good resolution. Pipeline ADC designed using 0.35 µm CMOS technology. Pipeline ADC successfully implemented in a electronics circuit and layout. It has been fabricated. The results of simulations show that the design of pipeline ADC is working properly and can be used to handle a high speed CMOS sensor that has speed of 10 000 frames/s.

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CMOS Pixel-Level ADC with Change Detection

Cited by 5 publications

References 6 publications

A 1,000 Frames/s Programmable Vision Chip with Variable Resolution and Row-Pixel-Mixed Parallel Image Processors

A 1,000 Frames/s Programmable Vision Chip with Variable Resolution and Row-Pixel-Mixed Parallel Image Processors

Video Sensor Node for Low-Power Ad-hoc Wireless Networks

Design and Implemention of ADC Implanted in 10 000Frame/s High-Speed CMOS Sensor

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