CMOS scaling for high performance and low power-the next ten years

Abstract

A guideline for scaling of CMOS technology for logic applications such as microprocessors is presented covering the next ten years, assuming that the lithography and base process development driven by DRAM continues on the same three-year cycle as in the past. This paper emphasizes the importance of optimizing the choice of power-supply voltage. Two CMOS device and voltage scaling scenarios are described, one optimized for highest speed and the other trading offspeed improvement for much lower power. It is shown that the low power scenario is quite close to the original constant electric-field scaling theory. CMOS technologies ranging from 0.25 pm channel length at 2.5 V down to sub-0.1 p m at 1 V are presented and power density is compared for the two scenarios. Scaling of the threshold voltage along with the powersupply voltage will lead to a substantial rise in standby power compared to active power, and some tradeoffs of performance andor changes in design methods must be made. Key technology elements and their impact on scaling are discussed.It is shown that a speed improvement of about 7x and over two orders of magnitude improvement in power-delay product (mW/MlPS) are expected by scaling of bulk CMOS down to the sub-0.1 pm regime as compared with today's high performance 0.6 p m devices at 5 V. However, the power density rises by a factor of 4 X for the high-speed scenario. The status of the siliconon-insulator (Sol) approach to scaled CMOS is also reviewed, showing the potential for about 3x savings in power compared to the bulk case at the same speed.

The impact of self-heating and SiGe strain-relaxed buffer thickness on the analog performance of strained Si nMOSFETs

“…Scaling V DD is essential in CMOS because the high lateral electric field caused by aggressive gate length scaling has a negative impact on device reliability and also because of the rapidly increasing power density in very large scale integration applications [30]. Power supply scaling is even more important in some mixed signal wireless circuits where battery life is critical.…”

Quantitative analysis of very-low-voltage testing

“…One of the trends in today's IC market is to reduce the supply voltage [16] [17]. The effectiveness of VLV testing is based on the observation that the difference of the electrical characteristics between a faulty circuit and a faultfree circuit can be increased by reducing the supply voltage.…”

“…The discussion in Section 2 concludes that the supply voltage for VLV testing should be in the range of 2V t to 2.5V t . For high performance CMOS designs, the threshold voltage is reduced so that the designs will not have severe speed degradation [15] [17]. Mii et al showed that there will be excessive delays if V t > V dd /4.…”

Transport properties and electrical device characteristics with the TiMeS computational platform: Application in silicon nanowires

“…7,8 Direct source-drain quantum mechanical tunneling 3,9 and gate-tunneling leakage arise, 10 obstructing the way to reducing power consumption. 11,12 Manifestations of differing properties of nanoscale materials compared to their bulk counterparts have also been demonstrated. For the prototypical material of silicon nanowires, surface functionalization schemes result in tuning the electronic and transport properties, [13][14][15] the effective masses of charge carriers become heavier, 16 dopants may deactivate, 17 and the deformation potentials and electron-phonon scattering can become highly anisotropic.…”