A guideline for scaling of CMOS technology for logic applications such as microprocessors is presented covering the next ten years, assuming that the lithography and base process development driven by DRAM continues on the same three-year cycle as in the past. This paper emphasizes the importance of optimizing the choice of power-supply voltage. Two CMOS device and voltage scaling scenarios are described, one optimized for highest speed and the other trading offspeed improvement for much lower power. It is shown that the low power scenario is quite close to the original constant electric-field scaling theory. CMOS technologies ranging from 0.25 pm channel length at 2.5 V down to sub-0.1 p m at 1 V are presented and power density is compared for the two scenarios. Scaling of the threshold voltage along with the powersupply voltage will lead to a substantial rise in standby power compared to active power, and some tradeoffs of performance andor changes in design methods must be made. Key technology elements and their impact on scaling are discussed.It is shown that a speed improvement of about 7x and over two orders of magnitude improvement in power-delay product (mW/MlPS) are expected by scaling of bulk CMOS down to the sub-0.1 pm regime as compared with today's high performance 0.6 p m devices at 5 V. However, the power density rises by a factor of 4 X for the high-speed scenario. The status of the siliconon-insulator (Sol) approach to scaled CMOS is also reviewed, showing the potential for about 3x savings in power compared to the bulk case at the same speed.

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We demonstrate a 0.08 pm CMOS suitable for highperformance (vdd=1.8 V) and low-power applications (vdd < 1.5 V) with the best current drive at a given off-current reported in the literature to date. Excellent short-channel effects were obtained for Leff down to 0.06 pm in the NFET and 0.08 pm in the PFET. Aggressive lateral and vertical dopant engineering allow the V, to be reduced with no degradation in short-channel effects resulting in a 50% improvement in delay at Vd,=l V over the regular-VT process. INTRODUCTION AND DESIGN CRITERIADevice channel lengths are continually scaled to improve circuit performance and packing density. In addition to performance, the emergence of battery-powered applications have emphasized the need for good low-voltage operation. The primary goal for a high-performance sub-0.1 pm device design is to achieve the highest current drive for a given amount of short-channel effect or off-current. At reduced supply voltages, the threshold voltage must also be scaled to maintain adequate performance [l]. To maximize the functionality of a technology, the device design should be suitable for both high-performance and low-power applications with minor modifications. A major challenge is to maintain good short-channel effects in the low-v, case. To achieve these design goals, the following features are used: 1) super-steep retrograde channel; 2) different V,' s for highperformance and low-voltage applications by altering the channel dose; 3) 3.5 nm N 2 0 gate dielectric to improve performance and prevent boron penetration in the PFET; and (4) aggressive lateral dopant engineering to achieve good short-channel effects even at low V,'S.