CMOS tunable TIA for 1.25 Gbit/s optical gigabit Ethernet

Pozo, José; Celma, S.; Sanz, M.T.; Alegre, J.P.

doi:10.1049/el:20071880

Cited by 14 publications

(6 citation statements)

References 4 publications

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“…The usual figure of merit in preamplifiers, C, is defined by the ratio of the product transresistance-bit rate and the product power-noise. A more advanced technology allows for reducing the power consumption and increasing the bandwidth, thus obtaining higher C. This fact must be taken into account when comparing the results of this work and those presented in [6] and [12]. The comparison shows a consistent performance evolution due to technology downscaling.…”

Section: Resultsmentioning

confidence: 69%

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2.5 Gb/s CMOS preamplifier for low-cost fiber-optic receivers

Pozo

Serdijn

Otín

et al. 2010

Analog Integr Circ Sig Process

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This paper reports an optical preamplifier intended for low-cost fiber-optic receivers. The preamplifier is based on a resistive shunt-feedback topology, is poweroptimized and employs two different frequency compensation techniques, phantom zeros and shunt-peaking. The circuit is designed in a 1.8 V 0.18 lm CMOS technology. Experimental results report a transresistance of 58 dBX and a bandwidth of 1.5 GHz, respectively. Eye diagrams obtained at 2.5 Gb/s show a total jitter of 18 ps and a bit error rate (BER) of 10 -12 when the input current amplitude (I in ) is equal to or higher than 8.5 lA. Higher bit rates up to 3 Gb/s also have been tested achieving a BER of 10 -12 when I in C9.5 lA. The power consumption and die active area are 23.7 mW and 0.017 mm 2 , respectively.

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Section: Resultsmentioning

confidence: 69%

“…However, making the openloop gain of the active part high enough, the transresistance depends only on R F and can thus be set accurately [6]. Therefore, the active part should employ two stages, one optimized for noise and the other optimized for bandwidth.…”

Section: Proposed Preamplifiermentioning

confidence: 99%

2.5 Gb/s CMOS preamplifier for low-cost fiber-optic receivers

Pozo

Serdijn

Otín

et al. 2010

Analog Integr Circ Sig Process

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“…The top structure of the proposed novel TIA is illustrated in Figure 2 . The core of the TIA is formed by three push-pull inverting amplifiers, which have been well examined previously [ 10 , 11 ]. The core of the TIA is modified to involve standby circuitry for portability aid which results in an almost zero off-current.…”

Section: Dual-mode Adjustable Gain Low Noise Tia With Indirect Feedback Biasingmentioning

confidence: 99%

“…Gain modes of the TIA are controlled based on an Indirect Operating Point Biasing (IOPB) technique. As is discussed in [ 10 , 11 ], the gain of a TIA with such a structure can change by changing the bias voltage of the feedback transistor. The importance of the fully digitally controlled amplifier is evident when the target is a well-controlled flexible hardware implementation, following various controller software scenarios.…”

Section: Dual-mode Adjustable Gain Low Noise Tia With Indirect Feedback Biasingmentioning

confidence: 99%

A 77-dB Dynamic-Range Analog Front-End for Fine-Dust Detection Systems with Dual-Mode Ultra-Low Noise TIA

Rad

Hejazi

Asl

et al. 2021

Sensors

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This paper presents an analog front-end for fine-dust detection systems with a 77-dB-wide dynamic range and a dual-mode ultra-low noise TIA with 142-dBΩ towards the maximum gain. The required high sensitivity of the analog signal conditioning path dictates having a high sensitivity at the front-end while the Input-Referred Noise (IRN) is kept low. Therefore, a TIA with a high sensitivity to detected current bio-signals is provided by a photodiode module. The analog front end is formed by the TIA, a DC-Offset Cancellation (DCOC) circuit, a Single-to-Differential Amplifier (SDA), and two Programmable Gain Amplifiers (PGAs). Gain adjustment is implemented by a coarse-gain-step using selective loads with four different gain values and fine-gain steps by 42 dB dynamic range during 16 fine steps. The settling time of the TIA is compensated using a capacitive compensation which is applied for the last stage. An off-state circuitry is proposed to avoid any off-current leakage. This TIA is designed in a 0.18 µm standard CMOS technology. Post-layout simulations show a high gain operation with a 67 dB dynamic range, input-referred noise, less than 600 fA/√Hz in low frequencies, and less than 27 fA/√Hz at 20 kHz, a minimum detectable current signal of 4 pA, and a 2.71 mW power consumption. After measuring the full path of the analog signal conditioning path, the experimental results of the fabricated chip show a maximum gain of 142 dB for the TIA. The Single-to-Differential Amplifier delivers a differential waveform with a unity gain. The PGA1 and PGA2 show a maximum gain of 6.7 dB and 6.3 dB, respectively. The full-path analog front-end shows a wide dynamic range of up to 77 dB in the measurement results.

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“…The conventional TIA structure or its improved versions [6,7] provide very good linearity and sensitivity but are limited in our application due to very low supply voltage. Therefore, we propose a preamplifier as that shown in Fig.…”

Section: A Transimpedance Amplifiermentioning

confidence: 99%

A 1-V CMOS receiver front-end for high-speed SI-POF links

Gimeno

Aldea

Celma

et al. 2012

2012 IEEE International Symposium on Circuits and Systems

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This paper presents a new analog front-end for short-reach high-speed optical communications. It compensates the limited bandwidth of SI-POF transmission systems. In particular, the front end has been designed using a cost-effective 0.18-µm CMOS technology and fed with only 1V. The proposed architecture, formed by a transimpedance amplifier and a continuous-time equalizer, targets 1.25 Gb/s transmission for a simple NRZ modulation in an optical link composed of 50 m of SI-POF and a large area Si PIN photodetector.

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CMOS tunable TIA for 1.25 Gbit/s optical gigabit Ethernet

Cited by 14 publications

References 4 publications

2.5 Gb/s CMOS preamplifier for low-cost fiber-optic receivers

2.5 Gb/s CMOS preamplifier for low-cost fiber-optic receivers

A 77-dB Dynamic-Range Analog Front-End for Fine-Dust Detection Systems with Dual-Mode Ultra-Low Noise TIA

A 1-V CMOS receiver front-end for high-speed SI-POF links

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