CNTFET Modeling and Reconfigurable Logic-Circuit Design

O’Connor, Ian; Junchen, Liu; Gaffiot, F.; Prégaldiny, F.; Lallement, Christophe; Maneux, Cristell; Goguet, Johnny; Fregonèse, Sébastien; Zimmer, Thomas; Anghel, Lorena; Dang, T.; Leveugle, Régis

doi:10.1109/tcsi.2007.907835

Cited by 153 publications

(101 citation statements)

References 27 publications

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“…Drawbacks to SB-CNFETs include bipolar features that limit the usage of these transistors in traditional CMOS-like types. This connection restricts transconductance in the ON status; therefore, it reduces Ion/Ioff by a relative amount [5]. A schematic diagram of a SB-CNFET is illustrated in Figure 1b.…”

Section: Cnfet Reviewmentioning

confidence: 99%

A CNFET full adder cell design for high-speed arithmetic units

Ghanatghestani¹,

Ghavami²,

Salehpour³

2017

Turk J Elec Eng & Comp Sci

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Carbon nanotube field-effect transistors (CNFETs) utilize an array of carbon nanotubes as the channel material instead of bulk silicon in the traditional MOSFET structure, which holds great promise for the future of integrated circuits. In this paper, a full adder cell based on a parallel design using CNFETs is presented. The main objective of designing this full adder cell is to reduce critical path delay in CNFET-based adder circuits. The proposed design positively affects speed and power consumption by shortening the data path. In order to evaluate the proposed design, several simulations were performed with different load capacitors, frequencies, and temperatures using HSPICE in 32-nm CMOS and 32-nm CNFET technologies. The proposed full adder cells were compared with five other full adder cells using 4-bit ripple carry adder (RCA) and 8-bit RCA circuits with power consumption, speed, and power delay product parameters. The obtained results indicate that the proposed design is faster than other designs due to a shortened data path. The results of the simulations confirm the higher efficiency of the proposed full adder cell with respect to other designs.

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Section: Cnfet Reviewmentioning

confidence: 99%

A CNFET full adder cell design for high-speed arithmetic units

Ghanatghestani¹,

Ghavami²,

Salehpour³

2017

Turk J Elec Eng & Comp Sci

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“…In [3] and [13], a compact in-field reconfigurable logic gate that maps eight different logic functions of two inputs using only seven CNTFETs in dynamic logic was presented. A full adder and an arithmetic logic unit (ALU) were designed using this reconfigurable logic gate in [14].…”

Section: Previous Design Approaches With Ambipolar Devicesmentioning

confidence: 99%

“…A method has been presented in [3]: every ambipolar CNTFET can be replaced by two parallel MOSFET-like …”

Section: Area and Delay Of Logic Gatesmentioning

confidence: 99%

“…A back gate can be used in order to control the device polarity. It has been shown recently that the unique property of in-field polarity control can yield denser and faster design of reconfigurable logic circuits [2], [3].…”

mentioning

confidence: 99%

“…In [2], generalized NOR (GNOR) gates, combining NOR and XOR operations, were described. In [3], the investigation of the potentials of ambipolar logic gates was restricted to the characterization of a single universal reconfigurable 8-function gate. The intrinsic reason for the high expressive power lies in the presence of an inverting device behavior (as, for example, a p-device in the pulldown network or vice versa) enabling the realization of binate functions in single logic gates.…”

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confidence: 99%

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An Efficient Gate Library for Ambipolar CNTFET Logic

Ben-Jamaa

Mohanram

Micheli

2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Recently, several emerging technologies have been reported as potential candidates for controllable ambipolar devices. Controllable ambipolarity is a desirable property that enables the on-line configurability of n-type and p-type device polarity. In this paper, we introduce a new design methodology for logic gates based on controllable ambipolar devices, with an emphasis on carbon nanotubes as the candidate technology. Our technique results in ambipolar gates with a higher expressive power than conventional complementary metal-oxidesemiconductor (CMOS) libraries. We propose a library of static ambipolar carbon nanotube field effect transistor (CNTFET) gates based on generalized NOR-NAND-AOI-OAI primitives, which efficiently implements XOR-based functions. Technology mapping of several multi-level logic benchmarks that extensively use the XOR function, including multipliers, adders, and linear circuits, with ambipolar CNTFET logic gates indicates that on average, it is possible to reduce the number of logic levels by 42%, the delay by 26%, and the power consumption by 32%, resulting in a energy-delay-product (EDP) reduction of 59% over the same circuits mapped with unipolar CNTFET logic gates. Based on the projections in [1], where it is stated that defectfree CNTFETs will provide a 5× performance improvement over metal-oxide-semiconductor field effect transistors, the ambipolar library provides a performance improvement of 7×, a 57% reduction in power consumption, and a 20× improvement in EDP over the CMOS library.

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Investigations on Field‐Effect Transistors Based on Two‐Dimensional Materials

et al. 2017

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In the present article, experimental and theoretical investigations regarding field-effect transistors based on two-dimensional (2D) materials are presented. First, the properties of contacts between a metal and 2D material are discussed. To this end, metal-to-graphene contacts as well to transition metal dichalcogenides (TMD) are studied. Whereas metal-graphene contacts can be tuned with an appropriate back-gate, metal-TMD contacts exhibit strong Fermi level pinning showing substantially limited maximum possible drive current. Next, tungsten diselenide (WSe 2 ) field-effect transistors are presented. Employing buried-triple-gate substrates allows tuning source, channel and drain by applying appropriate gate voltages so that the device can be reconfigured to work as n-type, p-type and as so-called band-to-band tunnel field-effect transistor on the same WSe 2 flake.

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CNTFET Modeling and Reconfigurable Logic-Circuit Design

Cited by 153 publications

References 27 publications

A CNFET full adder cell design for high-speed arithmetic units

A CNFET full adder cell design for high-speed arithmetic units

An Efficient Gate Library for Ambipolar CNTFET Logic

Investigations on Field‐Effect Transistors Based on Two‐Dimensional Materials

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