Code density optimization for embedded DSP processors using data compression techniques

Liao, Stan; Devadas, Srinivas; Keutzer, Kurt

doi:10.1109/43.709398

Cited by 33 publications

(19 citation statements)

References 10 publications

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“…More recently, the issue of optimal storage allocation has been examined in the context of high-level synthesis for iterative DSP programs [11], and code generation for embedded processors that have highly irregular instruction formats and register sets [7], [12]. For irregular embedded processors, code generation techniques have also been developed for the purpose of minimizing the amount of memory required to store a program's code [13], [14]. However, because of their focus on fine-grain scheduling, the above efforts apply to a homogeneous dataflow model-i.e., a model in which each computation (dataflow vertex) produces and consumes a single value to/from each incident edge.…”

Section: Related Workmentioning

confidence: 99%

Evolutionary algorithms for the synthesis of embedded software

Zitzler

Teich

Bhattclcharyya

2000

IEEE Trans. VLSI Syst.

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This paper addresses the problem of trading off between the minimization of program and data memory requirements of single-processor implementations of dataflow programs. Based on the formal model of synchronous dataflow (SDF) graphs [1], so-called single appearance schedules are known to be program-memory optimal. Among these schedules, buffer memory schedules are investigated and explored based on a two-step approach: 1) An evolutionary algorithm (EA) is applied to efficiently explore the (in general) exponential search space of actor firing orders; 2) For each order, the buffer costs are evaluated by applying a dynamic programming post-optimization step (GDPPO). This iterative approach is compared to existing heuristics for buffer memory optimization.Index Terms-Dataflow, evolutionary algorithms, memory management, software synthesis.

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Section: Related Workmentioning

confidence: 99%

Evolutionary algorithms for the synthesis of embedded software

Zitzler

Teich

Bhattclcharyya

2000

IEEE Trans. VLSI Syst.

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“…As shown in Figure 1, compressed code is stored in the external memory, and CodePack is placed between memory and cache. Liao [2] and Lefurgy [3] replaced frequently used instruction groups into dictionary entries, which make compressed code easy to be decoded. Lekatsas and Wolf [5] proposed SAMC, a statistical scheme based on arithmetic coding and Markov model.…”

Section: Previous Workmentioning

confidence: 99%

“…It refers to compress the program off-line and decompress it on-the-fly during execution. The idea was first proposed by Wolfe and Chanin in the early 90's [1], and many researches have been done to reduce the code size for RISC machines [2,3,4,5]. As instruction level parallelism (ILP) becomes the trend, a high-bandwidth instruction fetch mechanism is required to supply multiple instructions per cycle.…”

Section: Introductionmentioning

confidence: 99%

LZW-based code compression for VLIW embedded systems

Lin¹,

Xie²,

Wolf³

Proceedings Design, Automation and Test in Europe Conference and Exhibition

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We propose a new variable-sized-block method for VLIW code compression. Code compression traditionally works on fixed-sized blocks and its efficiency is limited by the small block size. Branch blocks -instructions between two consecutive possible branch targets -provide larger blocks for code compression. We propose LZW-based algorithms to compress branch blocks. Our approach is fully adaptive and generates coding table on-the-fly during compression and decompression. When encountering a branch target, the coding table is cleared to ensure correctness. Decompression requires only a simple lookup and update when necessary. Our method provides 8 bytes peak decompression bandwidth and 1.82 bytes in average. Compared to Huffman's 1 byte and V2F's 13-bit peak performance, our methods have higher decoding bandwidth and comparable compression ratio. Parallel decompression could also be applied to our methods, which is more suitable for VLIW architecture.

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“…Liao et a1. [8] and Bird and Mudge [9] proposed dictionary methods, which make compressed code easy to be decompressed. Liao et al applied their compression techniques on code generated by TI'S TMS320C25 compiler and report an average compression ratio of 88.2%.…”

Section: Previous Workmentioning

confidence: 99%

“…State [0,8) In this way, modern VLIW architectures eliminate the need to pad many NOPs into the binary code for fixed-length instruction words in the conventional VLIW architectures, therefore allow for very flexible encoding format, which results in a high code density with minimum cost. It also implies that the dictionary-based code compression algorithms in [ …”

Section: Vliw Instruction Words Formatmentioning

confidence: 99%

A code decompression architecture for VLIW processors

Xie¹,

Wolf²,

Lekatsas³

Proceedings. 34th ACM/IEEE International Symposium on Microarchitecture. MICRO-34

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In embedded system design, memory has been one of the most restricted resources. Reducing program size has been an important goal when designing an embedded system. Most of the previous work on code compression has targeted RISC architectures. Recently VLIW processors became very populal; particularly for signal processing. Decompression speed is especially important for VLIW architectures given that the length of the instruction word is long. Furthermore, modern VLJW architectures use flexible instruction formats, which require new code compression approaches. Previous work has assumed that instruction positions within the long instruction word correspond to spec$cfinctional units. In contrast, our code compression algorithm is capable of compressing flexible instruction formats, where any functional unit can be used for any position in the instruction word. We demonstrate our methods by applying it to the TMS32OC6x architecture. We also compare two techniques for decompressing the VLJW instruction packet to reduce the decompression time. A fast parallel decompression architecture is described, which is implemented in TSMC 0.25 technology.

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Code density optimization for embedded DSP processors using data compression techniques

Cited by 33 publications

References 10 publications

Evolutionary algorithms for the synthesis of embedded software

Evolutionary algorithms for the synthesis of embedded software

LZW-based code compression for VLIW embedded systems

A code decompression architecture for VLIW processors

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