Code generation from a domain-specific language for C-based HLS of hardware accelerators

Reiche, Oliver; Schmid, Moritz; Hannig, Frank; Membarth, Richard; Teich, Jürgen

doi:10.1145/2656075.2656081

Cited by 31 publications

(13 citation statements)

References 10 publications

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“…The two prior projects most similar to our effort, Darkroom [13,4] and HIPAcc [29], both created image processing DSLs and provided compiler tools using a line buffered pipeline microarchitecture to guide their hardware generation. They demonstrated it was possible to take a function coded in a DSL and implement it as an FPGA or ASIC.…”

Section: Image Dslsmentioning

confidence: 99%

Programming Heterogeneous Systems from an Image Processing DSL

Bell

Yang

et al. 2017

ACM Trans. Archit. Code Optim.

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Specialized image processing accelerators are necessary to deliver the performance and energy efficiency required by important applications in computer vision, computational photography, and augmented reality. But creating, "programming,"and integrating this hardware into a hardware/software system is difficult. We address this problem by extending the image processing language Halide so users can specify which portions of their applications should become hardware accelerators, and then we provide a compiler that uses this code to automatically create the accelerator along with the "glue" code needed for the user's application to access this hardware. Starting with Halide not only provides a very high-level functional description of the hardware, but also allows our compiler to generate the complete software program including the sequential part of the workload, which accesses the hardware for acceleration. Our system also provides high-level semantics to explore different mappings of applications to a heterogeneous system, with the added flexibility of being able to map at various throughput rates.We demonstrate our approach by mapping applications to a Xilinx Zynq system. Using its FPGA with two low-power ARM cores, our design achieves up to 6× higher performance and 38× lower energy compared to the quad-core ARM CPU on an NVIDIA Tegra K1, and 3.5× higher performance with 12× lower energy compared to the K1's 192-core GPU.

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Section: Image Dslsmentioning

confidence: 99%

Programming Heterogeneous Systems from an Image Processing DSL

Bell

Yang

et al. 2017

ACM Trans. Archit. Code Optim.

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“…There is also another body of work that focus on a different class of stencil applications where the number of time iterations are small [8], [9], [21]. Many image processing applications only make one pass over the image, but multiple of these filters may be composed to form an image processing pipeline.…”

Section: Stencil Computations On Fpgasmentioning

confidence: 99%

“…Earlier attempts targeting FPGAs showed that the performance of such accelerators is a complex interplay between the raw FPGA computing power, the amount of on-chip memory, and the performance of the external memory system [1]- [8]. They also illustrate different application requirements.…”

Section: Introductionmentioning

confidence: 99%

One size does not fit all: Implementation trade-offs for iterative stencil computations on FPGAs

Deest

Yuki²,

Rajopadhye³

et al. 2017

2017 27th International Conference on Field Programmable Logic and Applications (FPL)

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We generate a family of FPGA stencil accelerators targeting emerging System on Chip platforms, (e.g., Xilinx Zynq or Intel SoC). Our designs come with design knobs to explore trade-offs. We also propose performance models to hone in on the most interesting design points, and show how they accurately lead to optimal designs. The optimal choice depends on problem sizes and performance goals. I. INTRODUCTIONIterative stencil computations arise in many application domains, ranging from medical imaging to numerical simulation. Since they are computationally demanding, a large body of work addressed the problem of parallelizing and optimizing stencils for multi-cores, GPUs, and FPGAs.Earlier attempts targeting FPGAs showed that the performance of such accelerators is a complex interplay between the raw FPGA computing power, the amount of on-chip memory, and the performance of the external memory system [1]- [8]. They also illustrate different application requirements. For example, in the context of embedded vision, designers often seek the cheapest design achieving real-time performance constraints (e.g., 4K@60fps). In an exascale context, they may want to maximize performance (measured in ops-persecond) for a given FPGA board, while maintaining power dissipation to a minimum. Therefore, we explore a family of design options that can accommodate a large set of constraints, by exposing trade-offs between computing power, bandwidth requirements, and FPGA resource usage. We focus on system-level issues. Our aim is not to provide hand-optimized FPGA implementations. We have developed a code generator that produces HLS-optimized C/C++ descriptions of accelerator instances, leaving low-level decisions to the HLS back-end.Our designs build upon the tiling transformation, that we use to balance on-chip memory cost and off-chip bandwidth. The design space we explore can be characterized by the following design knobs.

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“…These hardware architectures are able to commence processing of the image as soon as the necessary pixels are received and continue processing the rest of the arriving image as a pipeline, giving rise to both low-latency and high-throughput operations. Indeed, to facilitate the design of complex streaming image-processing hardware, some FPGA-hardware generators have already been proposed, often relying on the use of domain-specific languages (DSLs) as a bridge between the algorithm designer and the lower-level hardware [ 5 , 6 , 7 , 8 ]. In our previous work, SWIM [ 9 ], a streaming line buffer generator, was also proposed to address the complexities of rearranging misaligned multi-pixel blocks for ultra high-input throughput applications.…”

Section: Introductionmentioning

confidence: 99%

“…Previous works presented general methods for designing a streaming architecture for image processing with a 2D access pattern [ 5 , 7 , 10 ]. Figure 1 shows an example.…”

Section: Introductionmentioning

confidence: 99%

High-Throughput Line Buffer Microarchitecture for Arbitrary Sized Streaming Image Processing

Shi¹,

Wong²,

So³

2019

J. Imaging

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Parallel hardware designed for image processing promotes vision-guided intelligent applications. With the advantages of high-throughput and low-latency, streaming architecture on FPGA is especially attractive to real-time image processing. Notably, many real-world applications, such as region of interest (ROI) detection, demand the ability to process images continuously at different sizes and resolutions in hardware without interruptions. FPGA is especially suitable for implementation of such flexible streaming architecture, but most existing solutions require run-time reconfiguration, and hence cannot achieve seamless image size-switching. In this paper, we propose a dynamically-programmable buffer architecture (D-SWIM) based on the Stream-Windowing Interleaved Memory (SWIM) architecture to realize image processing on FPGA for image streams at arbitrary sizes defined at run time. D-SWIM redefines the way that on-chip memory is organized and controlled, and the hardware adapts to arbitrary image size with sub-100 ns delay that ensures minimum interruptions to the image processing at a high frame rate. Compared to the prior SWIM buffer for high-throughput scenarios, D-SWIM achieved dynamic programmability with only a slight overhead on logic resource usage, but saved up to 56 % of the BRAM resource. The D-SWIM buffer achieves a max operating frequency of 329.5 MHz and reduction in power consumption by 45.7 % comparing with the SWIM scheme. Real-world image processing applications, such as 2D-Convolution and the Harris Corner Detector, have also been used to evaluate D-SWIM’s performance, where a pixel throughput of 4.5 Giga Pixel/s and 4.2 Giga Pixel/s were achieved respectively in each case. Compared to the implementation with prior streaming frameworks, the D-SWIM-based design not only realizes seamless image size-switching, but also improves hardware efficiency up to 30 × .

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Code generation from a domain-specific language for C-based HLS of hardware accelerators

Cited by 31 publications

References 10 publications

Programming Heterogeneous Systems from an Image Processing DSL

Programming Heterogeneous Systems from an Image Processing DSL

One size does not fit all: Implementation trade-offs for iterative stencil computations on FPGAs

High-Throughput Line Buffer Microarchitecture for Arbitrary Sized Streaming Image Processing

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