Code Transformations for TLB Power Reduction

Abstract

The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB though small is frequently accessed, and therefore not only consumes significant energy, but also is one of the important thermal hot-spots in the processor. Recently, several circuit and microarchitectural implementations of TLBs have been proposed to reduce TLB power. One simple, yet effective TLB design for power reduction is the Use-Last TLB architecture proposed in IEEE J Solid State Circuits, 1190-1199, (2004). The Use-Last TLB architecture reduces the power consumption when the last page is accessed again. In this work, we develop code transformation techniques to reduce the page switchings in data cache accesses and propose an efficient page-aware code placement technique to enhance the energy reduction capabilities achieved by the Use-Last TLB architecture for instruction cache accesses. Our comprehensive page switch reduction algorithm results in an average of 39% reduction in the data-TLB page switching, and our code placement heuristic results in an average of 76% reduction in the instrucion-TLB page switchings with negligible impact on the performance on benchmarks from MiBench, Multimedia, DSPStone and BDTI suites. The reduced page switch count through our techniques achieves an equivalent power savings, above and beyond the reduction achieved by the Use-Last TLB architecture implementation.

FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture

“…Therefore, NOR CAM has a clear speed advantage over NAND. For many high-speed applications [24], [67], [68], and especially when the associative array is on the critical path as in a TLB [69], [70], [71], the speed penalty of a NAND implementation is too high, leaving the NOR implementation as a likely option. The novel CCAM bitcell and a FASTA tag array architecture, introduced in Section III, do not require precharge and feature a tree-like logic for resolving the long resistive paths.…”

A survey of techniques for architecting TLBs

“…To enhance the effectiveness of these techniques, compiler-based schemes have been proposed that seek to reduce page transitions and enhance the locality. 16,48,49,56 Further, among the works that reuse translations ( 3. TLB leakage energy can be reduced by using reconfiguration 5,41,45 and using non-volatile (ie, low-leakage) memory to design TLB.…”

“…31 4. TLB miss-rate can be lowered by increasing TLB reach (eg, by using superpages or variable page-size), by using prefetching, software caching, TLB partitioning and reducing flushing overhead ( Superpage or multiple page sizes 2,3,5-7,11,12,20,21,34,36-38,40,61-65 Software managed TLB 35,61,66,67 Software caching 32 Designing TLB with non-volatile memory 31 Reusing last translation 16,48,49,54,56,57,59,68,69 Use of compiler 16,28,48,49,56,58,59,67,70 Using memory region or semantic information 16,42,47,58 Using private and shared page information 1,29,39,[71][72][73][74] Use of speculation 6,18,58,63,75 TLB reconfiguration 5,41,45 TLB partitioning 76 Prefetching 3,…”