Column-Parallel Vision Chip Architecture for High-Resolution Line-of-Sight Detection Including Saccade

Abstract

SUMMARYAlthough the line-of-sight (LoS) is expected to be useful as input methodology for computer systems, the application area of the conventional LoS detection system composed of video camera and image processor is restricted in the specialized area, such as academic research, due to its large size and high cost. There is a rapid eye motion, so called 'saccade' in our eye motion, which is expected to be useful for various applications. Because of the saccade's very high speed, it is impossible to track the saccade without using high speed camera. The authors have been proposing the high speed vision chip for LoS detection including saccade based on the pixel parallel processing architecture, however, its resolution is very low for the large size of its pixel. In this paper, we propose and discuss an architecture of the vision chip for LoS detection including saccade based on column-parallel processing manner for increasing the resolution with keeping high processing speed.

Design and Preliminary Evaluation of High‐Speed Line‐of‐Sight Calculation CMOS Image Sensor

“…To measure the LoS of saccades with high accuracy, it is necessary to simultaneously achieve high resolution, high frame rate, and low latency. The authors of this study have investigated a so‐called “Vision Chip” as an architecture for a camera device provided with LoS calculation processing . In the Vision Chip, the image processing circuit is integrated on the same chip as the CMOS image sensor.…”

“…The authors of this study previously proposed an LoS calculation image sensor architecture in which the image processing feature, for an LoS calculation system having a column parallel configuration, is capable of achieving both high‐resolution and high‐speed processability is integrated in a CMOS image sensor, which is the light receiving element of a camera . We also developed and discovered the usefulness of an emulation system with a latency of one frame by combining a high‐speed camera and an FPGA .…”

CMOS image sensor for high speed and low latency eye tracking

“…Eye tracking is performed by calculating the line of sight (LoS), or the eye direction. The LoS can be calculated from the position of the pupil in the infrared image of the user's eye, which is observed as a black area [7,8], as shown in Fig. 1.…”

[Paper] Column-Parallel Architecture for Line-of-Sight Detection Image Sensor Based on Centroid Calculation

“…Centroid Calculation 3.1 Outline of the architecture Fig. 2 and Fig.3 show the designed the columnparallel architecture for the centroid calculation, to realize both the high resolution, such as VGA (640 x 480[pixels]) or above, and the high frame rate, such as 500[fps] or above 6) . The sum of the horizontal (X-) and the vertical (Y-) directions, ∑ x ∑ y can be separated into Y-direction (∑ y ) and X-direction (∑ x ), and Y-direction sum, ∑ y , can be calculated at the sequential readout step for entire rows independently in each column.…”