[Paper] Column-Parallel Architecture for Line-of-Sight Detection Image Sensor Based on Centroid Calculation

Kawakami, Hayato; Igarashi, Satoru; Sasaki, Yuta; Akita, Junichi

doi:10.3169/mta.2.161

Cited by 5 publications

(4 citation statements)

References 4 publications

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“…It is also notable that we can calibrate combining the pupil's center (including errors) and the actual LoS without configuring ROI to obtain the correct LoS. [10].…”

Section: Methodsmentioning

confidence: 99%

CMOS image sensor for high speed and low latency eye tracking

Akita

2018

IEICE Electron. Express

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Eye tracking, or detecting where the user is looking at, is expected as a new type of user interfaces, with including the phenomenon of rapid eye movement, so called saccade. However, real-time tracking of saccade is difficult with the conventional image processing systems for their long processing time and latency against the speed of saccade. In this paper, we describe the design of the CMOS image sensor for eye tracking with high speed and low latency capability, as well as its evaluation results.

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“…It is also notable that we can calibrate combining the pupil's center (including errors) and the actual LoS without configuring ROI to obtain the correct LoS. [10].…”

Section: Methodsmentioning

confidence: 99%

CMOS image sensor for high speed and low latency eye tracking

Akita

2018

IEICE Electron. Express

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“…Note that there are other dark regions other than the pupil such as the eyelashes, and so forth, but the area of the pupil is large and, as such, the position of the pupil can be obtained almost exactly by finding the center of gravity of the black pixel region in the horizontally elongated eye region that contains the eye. Additionally, when the LoS is directed upward or downward such that the pupil is hidden under an eyelid, or when the user has long eyelashes, the accuracy of the obtained center of gravity of the pupil region is negatively affected, but it is possible to eliminate the influence of these factors to a great extent by calibrating the device prior to taking measurements .…”

Section: Los Calculation Processing Algorithmmentioning

confidence: 99%

“…The authors of this study previously proposed an LoS calculation image sensor architecture in which the image processing feature, for an LoS calculation system having a column parallel configuration, is capable of achieving both high‐resolution and high‐speed processability is integrated in a CMOS image sensor, which is the light receiving element of a camera . We also developed and discovered the usefulness of an emulation system with a latency of one frame by combining a high‐speed camera and an FPGA .…”

Section: Introductionmentioning

confidence: 99%

Design and Preliminary Evaluation of High‐Speed Line‐of‐Sight Calculation CMOS Image Sensor

Yamamura

Akita

2018

Elect Comm in Japan

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SUMMARY Line‐of‐sight (LoS) calculation, or detecting where the user is looking at, is expected as a new type of user interfaces, with including the phenomenon of rapid eye movement, so‐called saccade. However, real‐time tracking of saccade is difficult with the conventional image processing systems for their long processing time and latency against the speed of saccade. In this paper, we describe the design of the high speed, low latency LoS calculation image sensor, as well as its preliminary evaluation results. This image sensor has a capability to track the saccade at high frame rate, and generate the LoS calculation results with minimum latency for real‐time tracking.

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“…Such systems enable a reduction in circuit scale by using a fast and simple algorithm optimized for high frame-rate processing [ 1 ]. Previous works on such vision systems and chips [ 1 , 2 , 3 , 4 ] have yielded low imaging performance due to large matrix-based processing elements (PE) [ 1 , 2 , 3 ] and low functionality of the limited-purpose column-parallel PE architecture [ 4 ], constraining vision-chip applications. Dynamic Vision Sensors (DVSs) [ 5 , 6 , 7 , 8 ] also enable remarkably high-speed detection of intensity changes by using event-based operation.…”

Section: Introductionmentioning

confidence: 99%

Design and Performance of a 1 ms High-Speed Vision Chip with 3D-Stacked 140 GOPS Column-Parallel PEs †

Nose¹,

Yamazaki²,

Katayama³

et al. 2018

Sensors

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We have developed a high-speed vision chip using 3D stacking technology to address the increasing demand for high-speed vision chips in diverse applications. The chip comprises a 1/3.2-inch, 1.27 Mpixel, 500 fps (0.31 Mpixel, 1000 fps, 2 × 2 binning) vision chip with 3D-stacked column-parallel Analog-to-Digital Converters (ADCs) and 140 Giga Operation per Second (GOPS) programmable Single Instruction Multiple Data (SIMD) column-parallel PEs for new sensing applications. The 3D-stacked structure and column parallel processing architecture achieve high sensitivity, high resolution, and high-accuracy object positioning.

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[Paper] Column-Parallel Architecture for Line-of-Sight Detection Image Sensor Based on Centroid Calculation

Cited by 5 publications

References 4 publications

CMOS image sensor for high speed and low latency eye tracking

CMOS image sensor for high speed and low latency eye tracking

Design and Preliminary Evaluation of High‐Speed Line‐of‐Sight Calculation CMOS Image Sensor

Design and Performance of a 1 ms High-Speed Vision Chip with 3D-Stacked 140 GOPS Column-Parallel PEs †

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