Combining fault tolerance and self repair at minimum cost in power and hardware

Abstract

Large-scale integrated circuits and systems fabricated in nano-technologies exhibit new and enhanced fault properties which limit both their reliability and their life time. Transient fault effects have found most attention so far. They must be handled by on-line check and fault compensation based on duplication and triplication, typically at a significant amount of extra power. Such techniques are not suitable for life time extension, since their redundant elements all undergo wear-out effects in hot operation. Repair technologies that perform a process of system re-organization and introduction of cold redundancy may extend system life time, but they are too slow to catch and correct transient and permanent fault effects in hot operation. The essential task therefore remains to find methods and architectures that will provide on-line check in combination with self repair techniques at a minimum cost in extra power.

Timing for virtual TMR in logic circuits

“…Such schemes, also those involving triple execution on different units in a pseudo-TMR approach [18], inevitably perform a triplication of the computational processes, even in the fault-free condition, thus generating a significant amount of extra power consumption. If, however, delays of a few extra clock cycles can be accommodated, then a basic scheme of "virtual" triplication is possible, which is based on sharing redundancy between functions that use the same hardware resources [19]. Such schemes use only double hardware and power in the normal case, and they are well compatible with regular repair architectures.…”