Timing for virtual TMR in logic circuits

Abstract

Digital integrated circuits fabricated in nanotechnologies have first shown to be more vulnerable to transient errors effects than their predecessors. But they also show effects of stress-induced defects resulting in early life-time failures. In general, power dissipation problems and dielectric stress, due to high field strength, are the main reasons for shortened life-time expectations. On the other hand, system designers require highly reliable and long-time dependable hardware, for example in automotive applications. On-line error detection andcompensation using either codes or, in the more general case, double or triple modular redundancy (DMR and TMR), has been used for decades, but causes higher power dissipation in nano-logic, additional stress, and is therefore no cure in terms of life-time extension. Savings on hardware and power are possible, if resources can be re-allocated to produce local TMR upon demand. However, such techniques may cause sudden signal delays after the detection of errors, which are not easy to handle in synchronous systems. The paper makes an analysis of problems and shows first results in architectures for fast and efficient error detection and correction.

Validation of the Proposed Hardness Analysis Technique for FPGA Designs to Improve Reliability and Fault-Tolerance

“…The reliability of the FPGA systems is improved by various error mitigation schemes such as multiple-redundancy with voting, Triple Modular Redundancy (TMR), hardened memory cell level, and Error Detection And Correction (EDAC) coding. Among all SEU mitigation techniques, TMR has become the most common practice because of its straightforward implementation and reliable results [8], [2], [9], [10], [11]. These mitigation methods reduce the failure rate (SER) in combinational logic in integrated circuits and improve the reliability.…”

RASP-TMR: An Automatic and Fast Synthesizable Verilog Code Generator Tool for the Implementation and Evaluation of TMR Approach

“…The reliability of the FPGA systems is im-proved by various error mitigation schemes such as multipleredundancy with voting, Triple Modular Redundancy (TMR), hardened memory cell level, and Error Detection And Correction (EDAC) coding. Among all SEU mitigation techniques, TMR has become the most common practice because of its straightforward implementation and achieved the reliable results [6], [7], [8], [9]. The TMR mitigation scheme uses three identical logic circuits for performing the same task in parallel with corresponding outputs obtained through majority voters.…”