Compact Hardware Implementation of the Block Cipher Camellia with Concurrent Error Detection

Heys, Howard M.

doi:10.1109/ccece.2007.287

Cited by 5 publications

(2 citation statements)

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“…These results should be put in context by considering that a CED scheme based on hardware redundancy would require more that 100% area overhead. Similar studies for AES [5] and Camellia [6] found that compact implementations with CED resulted in 10.9k gates for AES and 26k gates for Camellia. C. Error Detection Capability The basic components of our compact architecture of ICEBERG are the XORs, S-boxes, registers, and multiplexers.…”

Section: Previous Implementationsmentioning

confidence: 66%

Compact ASIC Implementation of the ICEBERG Block Cipher with Concurrent Error Detection

Heys

2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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-ICEBERG is a block cipher that has been recently proposed for security applications requiring efficient FPGA implementations. In this paper, we investigate a compact ASIC implementation of ICEBERG and consider the novel application of concurrent error detection to protect the implementation from fault-based attacks. The compact architecture of ICEBERG requires about 5800 gates with a throughput of 552 Mbps in an ASIC implementation based on 0.18 µm CMOS technology. The addition of an effective multiple parity concurrent error detection scheme to protect the hardware from fault attacks results in a 62% area overhead.

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Section: Previous Implementationsmentioning

confidence: 66%

Compact ASIC Implementation of the ICEBERG Block Cipher with Concurrent Error Detection

Heys

2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…Different ASIC implementations of the Camellia algorithm have been reported in [10,[13][14][15][16][17][18][19][20][21][22][23][24]. In [18] compact and highspeed hardware2 architectures for the 128-bit AES and Camellia block ciphers are presented.…”

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confidence: 99%

Flexible and high‐throughput structures of Camellia block cipher for security of the Internet of Things

Rashidi

2021

IET Computers & Digital Tech

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The advancements in wireless communication have created exponential growth in the Internet of Things (IoT) systems. Security and privacy of the IoT systems are critical challenges in many data‐sensitive applications. Herein, high‐throughput and flexible hardware implementations of the Camellia block cipher for IoT applications are presented. In the proposed structures, sub‐blocks of the ciphers are implemented based on optimised circuits. The proposed structures for Camellia are designed and shared for implementing the encryption process and generating some intermediate key values in the two separate times. The most complex block in these ciphers is the substitution box (S‐box). The S‐boxes are implemented based on area‐optimised logic circuits. The Camellia S‐boxes consist of a field inversion over double-struckF28 and two affine transformations over double-struckF2. The inversion operation is implemented over the composite field double-struckF(24)2 instead of an inversion over double-struckF28 which is an important factor to reduce area consumption. A large number of gates, in the structure, have been implemented by 2‐input NAND and 2‐input NOR gates to reduce delay and area. Also, the flexible structure for Camellia that can do various configurations of this cipher to support variable key sizes 128, 192 and 256 bits was proposed. Implementation results of the proposed architectures in 180 nm CMOS technology for different key sizes are achieved. The results show improvements in terms of execution time, throughput and throughput/area compared to the other related works.

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Some Representations of the S-Box of Camellia in GF(((22)2)2)

Martínez-Herrera

Mex-Perera

Nolazco-Flores

2012

Cryptology and Network Security

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Compact Hardware Implementation of the Block Cipher Camellia with Concurrent Error Detection

Cited by 5 publications

References 10 publications

Compact ASIC Implementation of the ICEBERG Block Cipher with Concurrent Error Detection

Compact ASIC Implementation of the ICEBERG Block Cipher with Concurrent Error Detection

Flexible and high‐throughput structures of Camellia block cipher for security of the Internet of Things

Some Representations of the S-Box of Camellia in GF(((22)2)2)

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