Compact low swing gearbox-type integrated capacitive DC/DC converter

Abstract

A gearbox-type capacitive DC/DC converter is presented with an enhanced switch-and capacitor-array. The switch overhead is reduced significantly with respect to a conventional implementation. The presented topologies exhibit a lower swing on the intermediate capacitor nodes so that power loss due to the parasitic capacitances on these nodes is reduced drastically.Introduction: Each capacitive DC/DC converter topology has a dedicated voltage conversion ratio (VCR) for which it can operate in an efficient way. Gearbox-type capacitive DC/DC converters are converters comprising multiple topologies in order to extend the high efficiency of a converter over a broader output voltage range. By reconfiguring the converter during operation the output voltage range of such a converter is extended [1]. When selecting topologies for building a gearbox, we suggest three metrics: the parasitic swing metric (PS), the output impedance metric (OI) and the switch overhead metric (SO).

MIMO Switched-Capacitor DC–DC Converters Using Only Parasitic Capacitances Through Scalable Parasitic Charge Redistribution

“…For a single-output converter, different topologies can be evaluated by simply comparing their SSL topology factors, K c , to one another [13], [31]. These are in essence their SSL-resistance [28], but normalized for switch frequency and total flying capacitance [13].…”

Scalable Parasitic Charge Redistribution: Design of High-Efficiency Fully Integrated Switched-Capacitor DC–DC Converters

“…respectively, with V out the output voltage, K BP the topological capacitor node swing factor [19], α t the transistor capacitance per unit conductance and V trans the transistor voltage swing. Note that (7) assumes only one type of transistor is used and that V trans is equal for all transistors.…”

High-Ratio Voltage Conversion in CMOS for Efficient Mains-Connected Standby

“…Consequently, another metric M sw , introduced by [VB10], is required to capture this influence. Metric M sw , given in Eq.…”

“…The capacitance density of integrated capacitors heavily influences the realizable power density [And14b] [VP13] [Mey13c]. On top of that, M sw -associated losses have a large impact on the system efficiency as C par may be subject to very high voltage swing [VB10] [Mey14] and produce losses, as given by Eq 7.3.…”