Compact lumped element model for TSV in 3D-ICs

Rouby, Alaa El; Ragai, Hani; Amin, Karim; Ismail, Yehea

doi:10.1109/iscas.2011.5938067

Cited by 20 publications

(4 citation statements)

References 7 publications

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“…In our previous work [17]- [18], a lumped model for the TSV is proposed under the assumptions of an uniform doping. Here, the effects of non-uniform substrate doping profile on the electrical performance of a TSV are studied.…”

Section: Analysis and Resultsmentioning

confidence: 99%

Effect of non-uniform substrate doping profile on the electrical performance of through-silicon-via for low power application

Salah¹,

Rouby²,

Ragai

et al. 2012

2012 International Conference on Energy Aware Computing

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The effects of substrate doping density on the electrical performance of a TSV are investigated in this paper. The previously introduced lumped circuit model for TSV structure is used for a lightly-doped silicon structure. A new lumped circuit model based on the field distribution in a heavily-doped silicon substrate is proposed and its physical understanding is explained. Both circuit models for the lightly-doped and heavilydoped cases are validated using full-wave simulations up to 10 GHz.

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Section: Analysis and Resultsmentioning

confidence: 99%

Effect of non-uniform substrate doping profile on the electrical performance of through-silicon-via for low power application

Salah¹,

Rouby²,

Ragai

et al. 2012

2012 International Conference on Energy Aware Computing

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“…Fig. 10 compares the PE of C ox between the simulated and calculated results using (8) in this paper (PE1) and [22, eq. (4)] (PE2), respectively.…”

Section: A Verification Of the Insulator Capacitance Expressionmentioning

confidence: 99%

Capacitance Expressions and Electrical Characterization of Tapered Through- Silicon Vias for 3-D ICs

Wang

Zhang

2015

IEEE Trans. Compon., Packag. Manufact. Technol.

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Closed-form expressions of the parasitic insulator capacitance and the substrate capacitance for tapered throughsilicon vias (T-TSVs) are proposed. The expressions are suitable for TSVs with high aspect ratio (thin and long). The maximum percentage errors between the calculated and simulated results for the insulator capacitance and the substrate capacitance are 1.86% and 3.75%, respectively. Then the equivalent circuit model of the T-TSV signal-ground pair is established and validated by comparison with the full-wave simulation results. Furthermore, the electrical characteristics of the T-TSV are evaluated with the proposed expressions. The results indicate that the T-TSV has longer latency and less crosstalk than the cylindrical TSVs. Index Terms-Insulator capacitance, metal-oxidesemiconductor (MOS) effect, substrate capacitance, tapered through-silicon vias (T-TSVs).2156-3950 . Her current research interests include microwave and millimeter-wave integrated circuits, electromagnetic compatibility, and microstrip antenna.

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“…In addition, the substrate resistance depends on the number of body contacts surrounding the TSV. Its value may range from 1.5kΩ , when no body contacts surrounding the TSV, to 50Ω when the TSV it is surrounded by 4 body contacts [16]. Based on ITRS 2010 predictions [2], we used 50u TSV length in our experiments.…”

Section: Tsv Wire Modelmentioning

confidence: 99%

A case for 3D stacked analog circuits in high-speed sensing systems

Abdel-Majeed

Chen

Annavaram

2012

Thirteenth International Symposium on Quality Electronic Design (ISQED)

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In order to build high performance real-time sensing systems every building block in the system should be built with a technology that allows that building block to achieve its best performance. Technologies like BJT and BICMOS are better suited for building basic analog blocks like input buffers and power amplifiers, while CMOS is the best choice for digital data processing. To build mixed-technology systems traditionally system-in-package (SiP) techniques are used. SiP integration uses bonding wires or flip chip instead of on-chip integration. In this paper we study the feasibility of using 3D stacking to integrate heterogeneous blocks built using different technologies within a real-time sensing system. Several of the previous studies on 3D stacking focused on integrating multiple digital blocks and using through-silicon-vias (TSVs) to transfer digital signals between the layers in a stack. In this paper we study the behavior of the analog signals traversing through TSVs and measure how well 3D stacking can enhance or limit the performance of analog and digital stacking. In order to quantify the power and performance characteristics, we modeled bonding wire, flip chip, and through-silicon-via (TSV) interfaces. Using these models we show that 3D stacking of analog and analog/digital components can double the bandwidth, increase sampling frequency by nearly two orders magnitude and and improve the signal integrity by 3 dB compared to bond wires.

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Compact lumped element model for TSV in 3D-ICs

Cited by 20 publications

References 7 publications

Effect of non-uniform substrate doping profile on the electrical performance of through-silicon-via for low power application

Effect of non-uniform substrate doping profile on the electrical performance of through-silicon-via for low power application

Capacitance Expressions and Electrical Characterization of Tapered Through- Silicon Vias for 3-D ICs

A case for 3D stacked analog circuits in high-speed sensing systems

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