Compact Modeling of Graded N-Channel Independent Gate FET with Underlaps, Spacer and S/D Straggle for Low Power Application

Chattopadhyay, Ankush; Bose, Chayanika; Sarkar, Chandan Kumar

doi:10.1007/s12633-020-00424-2

Cited by 6 publications

(2 citation statements)

References 41 publications

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“…Due to shortening of channel length, gate tends to lose its control over the channel and the device, so subthreshold leakage current engenders [3,15,16] prompting abnormality in device performance. Hence, developing vertical FETs in the form of double-gate/tri-gate structures and integrating them with unconventional technologies (SOI, high-k, etc.)…”

Section: Introductionmentioning

confidence: 99%

“…Hence, developing vertical FETs in the form of double-gate/tri-gate structures and integrating them with unconventional technologies (SOI, high-k, etc.) are some of the alternatives that researchers are looking into since the last decade for augmentation of device performance at nanoscale [12,[14][15][16]. One of the promising device structure that surfaced in nano-regime having an additional gate on other side for better control over channel depletion region employing SOI technology is the double gate silicon-on-insulator (DGSOI) MOSFET, which avoids field penetration from source/drain to the substrate ensuing reduction in leakage enriching the output characteristics [17][18][19].…”

Section: Introductionmentioning

confidence: 99%

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Physics and Modelling of Tri-Layered Strained Channel for Development of Double Gate n-channel FET

Kumar

Dhar

2021

Preprint

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The strain silicon technology with FET is a dominant technology providing enrichment in carrier velocity in nanoscaled device by change of band structure arrangement. Leakage reduction while enhancement in drain current is another major objective therefore, designing a nano-regime double gate FET with strained channel is perceived. So, design and implementation of a double gate strained heterostructure on insulator (DG-SHOI) FET with tri-layered channel (s-Si/s-SiGe/s-Si) is the core. Biaxial strain is created in channel by inculcating three layers with optimal thicknesses while narrow channel depletion regions are strongly controlled by equipotential gates. Consequently, maximum charge carriers accumulate in channel due to quantum carrier confinement instigating ballistic transport across the 22 nm channel length device leading to lessening of intervalley scattering. In comparison to existing 22 nm DGSOI FET, drain current augmentation of 56% and transconductance amplification of 87.6% is observed while DIBL is prudently reduced for this newly designed and implemented DG-SHOI FET, signifying advancement in microelectronic technology.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Physics and Modelling of Tri-Layered Strained Channel for Development of Double Gate n-channel FET

Kumar

Dhar

2021

Preprint

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Analytical Modeling of Harmonic Distortions in GAA Junctionless FETs for Reliable Low-Power Applications

Chattopadhyay¹,

Chanda²,

Bose

et al. 2021

Journal of Elec Materi

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Analysis of Underlap Strained Silicon on Insulator MOSFET for Accurate and Compact Modeling

Sharma

Rana

Kaushal

et al. 2021

Silicon

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Recently, transistors with an underlapped gate structure have been widely studied to overcome several challenges associated with nanoscale devices. In this work, underlap region is incorporated at source and drain (S/D) ends in a fully depleted Strained Silicon On Insulator (SSOI) device, with high-k dielectric material in the spacer region. The S/D underlapped region helps to reduce the leakage current and can be particularly useful for low power applications.However, increased underlap length degrades the ON current significantly. We show that this issue can be mitigated via the inclusion of a high-k spacer, which improves the ON current by enhancing the gate controllability over the S/D underlap channel region. It helps to achieve the essential requirement low power applications i.e. the high ON/OFF current ratio at extremely low value of leakage current. The strained silicon material is used in the channel region to further improve the ON current. A compact threshold voltage model is developed for the proposed device (underlap-SSOI) while maintaining the accuracy at par with TCAD simulations. This threshold voltage model incorporates underlap length, strain-induced offsets and spacer dielectric constant. This device model may be used for circuit simulations.

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Compact Modeling of Graded N-Channel Independent Gate FET with Underlaps, Spacer and S/D Straggle for Low Power Application

Cited by 6 publications

References 41 publications

Physics and Modelling of Tri-Layered Strained Channel for Development of Double Gate n-channel FET

Physics and Modelling of Tri-Layered Strained Channel for Development of Double Gate n-channel FET

Analytical Modeling of Harmonic Distortions in GAA Junctionless FETs for Reliable Low-Power Applications

Analysis of Underlap Strained Silicon on Insulator MOSFET for Accurate and Compact Modeling

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