Comparative analysis of adiabatic logic challenges for low power CMOS circuit designs

Kumar, D. Sriram; Kumar, Manoj

doi:10.1016/j.micpro.2018.04.008

Cited by 9 publications

(2 citation statements)

References 14 publications

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“…There are different adiabatic techniques in the literature [5] In "Efficient Charge Recovery Logic (ECRL)" Logic, a pair of pull_down NMOS network and pull_up PMOS network forms the logic in ECRL. Both pre-charge and assessment(evaluation) are conducted concurrently in this technique.…”

Section: "Adiabatic Logic" Techniquesmentioning

confidence: 99%

Implementation of Energy Efficient gates using Adiabatic Logic for Low Power Applications

Anitha*¹

2019

IJRTE

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In today's electronic sector, low energy has appeared as a major feature. Power effectiveness is one of the most significant characteristics of contemporary, high-speed and mobile digital devices. Different methods are available to decrease energy dissipation at distinct stages of the planning method and have been applied. As the transistors count per device region continues to rise, while the switching energy does not rise at the same pace, power dissipation increases, and heat removal becomes more hard and costly. The power consumption of electronic appliances can be decreased by using various logic types. For such low-power electronic applications, adiabatic logic mode is very appealing. Using adiabatic logic, distinct powerefficient gates are intended in this document and contrasted for energy dissipation, propagation delay and no of the transistors used. In addition, the circuit developer can use these gates in the combinational and sequential circuits to develop low-power systems. The simulations of these gates are carried out in 90 nm technology using cadence virtuoso instrument.

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Section: "Adiabatic Logic" Techniquesmentioning

confidence: 99%

Implementation of Energy Efficient gates using Adiabatic Logic for Low Power Applications

Anitha*¹

2019

IJRTE

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“…The shrinking feature size of process technology has enhanced the potential performance of electronic devices, and the capacity of shift registers has increased significantly. Therefore, asking for less overhead integrated circuitry layout area [9][10][11][12] and less power consumption [9,11,[13][14][15][16][17][18][19][20][21][22][23][24][25][26] in the shift registers design then becomes more important with the capacity increasing [27].…”

Section: Introductionmentioning

confidence: 99%

A Novel Cross-Latch Shift Register Scheme for Low Power Applications

et al. 2020

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The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch.

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Withdrawn: Design of Adiabatic Circuits With Reversible Logic Based Full Adder and Multiplier in Current-Mode Logic Circuits for Efficient Power Dissipation

Kalamani¹,

Nishok²,

Asha³

et al. 2022

Optik

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Comparative analysis of adiabatic logic challenges for low power CMOS circuit designs

Cited by 9 publications

References 14 publications

Implementation of Energy Efficient gates using Adiabatic Logic for Low Power Applications

Implementation of Energy Efficient gates using Adiabatic Logic for Low Power Applications

A Novel Cross-Latch Shift Register Scheme for Low Power Applications

Withdrawn: Design of Adiabatic Circuits With Reversible Logic Based Full Adder and Multiplier in Current-Mode Logic Circuits for Efficient Power Dissipation

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