Comparative Analysis of Different Architectures of MCML Square Root Carry Select Adders for Low-Power Applications

Jain, Ginni; Vyas, Keerti; Maurya, Vijendra K; Patel, Mayank

doi:10.1007/978-981-10-0135-2_29

Cited by 1 publication

(1 citation statement)

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“…Rather than using dual ripple carry adders, a carry select adder may be built the use of a ripple-carry adder and an add-one circuit. Several adder structures [24] were proposed primarily based totally at the area, delay, and energy intake requirements. In analog design [25], the main parameters which are considered for the designs are area and power.…”

Section: Related Workmentioning

confidence: 99%

Efficient carry select 16-bit square root adder with complementary metal-oxide semiconductor implementation

Sathyanarayan

Mohan

Kakde

et al. 2022

IJEECS

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The adder is the maximum usually used mathematics block in programs inclusive of <span lang="EN-US">central processing unit (CPU) and virtual sign processing. As a result, it is important to expand a space-saving, low-strength, high-overall performance adder circuit. The hassle is diagnosed to layout mathematics sub structures with minimized strength dissipation, low area, and minimal time postpone of common-sense circuits. In conventional <a name="_Hlk95894088"></a>carry select adder (CSA), the time required to generate the sum output is less than other basic adder circuits but the principal difficulty is the location because the variety of transistors used to put in force the CSA circuit is fairly more. So, the area increases because of which the overall power consumption of the circuit will be more. If it's far viable to lessen the variety of transistors used withinside the structure of CSA adder, then, the strength intake of the circuit may be decreased or even the reaction time will improve. By lowering the area of the adder circuit, the suggested solution intends to reduce power consumption and latency.</span>

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Section: Related Workmentioning

confidence: 99%