Comparative analysis of nanoscale MOS device architectures for RF applications

Abstract

The suitability of nanoscale non-planar FinFETs and classical planar single and double gate SOI MOSFETs for rf applications is examined via extensive 3D device simulations and detailed interpretation. It is shown that although nanoscale FinFETs achieve higher values of intrinsic dc gain (nearly 20 dB higher than planar SG devices), they also present higher gate capacitance that severely undermines their rf performance. We also show that at large values of drain currents, well-designed conventional planar single and double gate SOI MOSFETs attain higher values of cut-off frequency compared to FinFETs, whereas at lower drain currents, a well-aligned planar double gate SOI MOSFET is the optimal structure. The reason for higher parasitic capacitance in FinFETs as compared to planar MOSFETs is examined in detail. An assessment of the impact of back gate misalignment on the rf performance of a 25 nm gate length planar double gate MOSFET indicates that a misalignment of 12 nm towards the source end is acceptable to give superior performance to a FinFET. The importance of source/drain extension region engineering in nanoscale FinFETs for ultra-low voltage analogue applications is also investigated. RF figures of merit for planar and vertical MOS devices are also compared based on layout-area calculations. The paper provides valuable design insights for optimizing device parameters for nanoscale planar and vertical MOSFETs.

How crucial is back gate misalignment/oversize in double gate MOSFETs for ultra-low-voltage analog/rf applications?

“…At higher drain currents i.e. above-threshold operation [33] and bias voltages, analog/ rf FOMs will not be symmetric with respect to ±m/L g due to the impact of resistance of the S/D extension regions. In this work, we are concentrating on ULV analog/rf applications where the device is biased in the weak and low moderate inversion regions.…”

“…The impact of back gate misalignment/oversize on device performance for above threshold operation i.e. at higher current levels, has been discussed separately [33]. S/D extension region engineered devices will not be useful for operation at higher current levels (>30 lA/lm), due to the additional parasitic series resistance that severely degrades the device performance.…”

Effects of Rapid Thermal Annealing Temperature on Performances of Nanoscale FinFETs

“…where, Si ε is the permittivity of the Si, s ψ is the surface potential and q is the electronic charge. Cut-off frequency [5] of a FinFET is defined as…”

“…Even, application of new channel materials and gate insulator cannot meet all the ITRS projections below 65 nm CMOS technology generation with conventional structures [2,3]. Nonclassical structures are emerging as potential solution to these technological roadblocks [4][5][6]. FinFET ( Fig.…”

Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies

“…FinFETs have enhanced control of short channel effects, higher source-drain series resistance and higher fringing capacitance [3] [4]. Mobility in a FinFET degrades due to the <110> orientation of the sidewalls.…”