Effects of Rapid Thermal Annealing Temperature on Performances of Nanoscale FinFETs

Sengupta, Mainak; Chattopadhyay, Sanatan; Maiti, C. K.

doi:10.5573/jsts.2009.9.4.266

Cited by 4 publications

(1 citation statement)

References 11 publications

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“…Implantation condition was arsenic 1 Â 10 15 cm À2 at 20 keV. To activate dopants, rapid thermal annealing (RTA) is applied at 1050 C, 5 s. 16) The inter-layer dielectric (ILD) of 5000 A ẘas deposited and contact holes are formed. After metallization, alloy was performed at 450 C in N 2 /H 2 ambient for 30 min.…”

Section: Fabrication and Measurementmentioning

confidence: 99%

Investigation of Field Concentration Effects in Arch Gate Silicon–Oxide–Nitride–Oxide–Silicon Flash Memory

Lee

Cho

et al. 2010

Jpn. J. Appl. Phys.

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In this paper, arch gate silicon–oxide–nitride–oxide–silicon (SONOS) flash memory is studied. The key technology for this device lies in making the device channel on an arch-shaped silicon fin. This feature enhances the electric field across the tunneling oxide by field concentration, and at the same time, reduces the field across the barrier oxide. Thus, when the high gate voltage is applied in the program operation, the tunneling current, and in turn, the program speed is drastically improved. The lowered electric field at the top oxide prohibits the electron back-tunneling from the polycrystalline silicon gate, which enables more reliable and faster erase operation. Full fabrication processes and the measurement results are presented in detail. The process and device simulation results are also given to confirm the critical electrostatic characteristics of the Arch SONOS flash memory device at each step and design the process integration.

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Section: Fabrication and Measurementmentioning

confidence: 99%

Investigation of Field Concentration Effects in Arch Gate Silicon–Oxide–Nitride–Oxide–Silicon Flash Memory

Lee

Cho

et al. 2010

Jpn. J. Appl. Phys.

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Introduction to Industrial Applications of Low Power Design Methodologies

Kim¹,

Lee²,

Choi³

et al. 2009

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Moore's law has driven silicon technology scale down aggressively, and it results in significant increase of leakage current on nano-meter scale CMOS. Especially, in mobile devices, leakage current has been one of designers' main concerns, and thus many studies have introduced low power methodologies. However, there are few studies to minimize implementation cost in the mixed use of the methodologies to the best of our knowledge. In this paper, we introduce industrial applications of low power design methodologies for the decrease of leakage current. We focus on the design cost reduction of power gating and reverse body bias when used together. Also, we present voltage scale as an alternative to reverse body bias. To sustain gate leakage current, we discuss the adoption of high-κ metal gate, which cuts gate leakage current by a factor of 10 in 32 nm CMOS technology. A 45 nm mobile SoC is shown as the case study of the mixed use of low power methodologies.Index Terms-Power gating, reverse body bias, hig h-κ metal gate, low power, leakage current

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Power Amplifiers and Transmitters for Next Generation Mobile Handsets

Choi¹,

Kang²,

Kim³

et al. 2009

JSTS:Journal of Semiconductor Technology and Science

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As a wireless handset deals with multiple application standards concurrently, RF transmitters and power amplifiers are required to be more power efficient and reconfigurable. In this paper, we review the recent advances in the design of the power amplifiers and transmitters. Then, the systematic design approaches to improve the performance with the digital baseband signal processing are introduced for the next generation mobile handset.

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Effects of Rapid Thermal Annealing Temperature on Performances of Nanoscale FinFETs

Cited by 4 publications

References 11 publications

Investigation of Field Concentration Effects in Arch Gate Silicon–Oxide–Nitride–Oxide–Silicon Flash Memory

Investigation of Field Concentration Effects in Arch Gate Silicon–Oxide–Nitride–Oxide–Silicon Flash Memory

Introduction to Industrial Applications of Low Power Design Methodologies

Power Amplifiers and Transmitters for Next Generation Mobile Handsets

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