Comparative analysis of various types of multipliers for effective low power

Shanmuganathan, Rajasree; Brindhadevi, Kathirvel

doi:10.1016/j.mee.2019.04.015

Cited by 25 publications

(19 citation statements)

References 20 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…From this structure, it is observed that N partial product rows can be added using the proposed N-operand BTA which involves log 2 N addition stages. Secondly, the M × N Wallace multiplier structure of [34] is analysed in which N partial product rows are generated in the same way as in array multiplier. Initially, these N partial product rows are reduced to two operands using carry-save adders (array of FAs) and finally these two operands are added by the RCA.…”

Section: Performance Analysis Of Proposed Bta In Multipliersmentioning

confidence: 99%

“…For this purpose, three recent multiplier structures, namely array multiplier [34], Wallace multiplier [34] and Booth multiplier [35] are analysed. Firstly, we have analysed

M \times N

array multiplier of [34] in which N partial product rows are generated using AND gates, where M and N denote the bit width of multiplicand and multiplier terms, respectively. These partial product rows are added in

false(N - 1 false)

number of addition stages to generate the final product.…”

Section: Performance Analysis Of Proposed Bta In Multipliersmentioning

confidence: 99%

“…Secondly, the

M \times N

Wallace multiplier structure of [34] is analysed in which N partial product rows are generated in the same way as in array multiplier. Initially, these N partial product rows are reduced to two operands using carry‐save adders (array of FAs) and finally these two operands are added by the RCA.…”

Section: Performance Analysis Of Proposed Bta In Multipliersmentioning

confidence: 99%

“…8 a and b , respectively. The use of the proposed BTA in multiplier structures has improved the ADP and EDP performance of the array multiplier of [34] by 69.35 and 70.5%; Wallace multiplier of [34] by 16.6 and 19.1%; Booth multiplier of [34] by 21.1 and 31.3%. Therefore, from the above discussion, it is clear that the proposed BTA can be used to improve the performance of multiplier designs.…”

Section: Performance Analysis Of Proposed Bta In Multipliersmentioning

confidence: 99%

See 3 more Smart Citations

Area–delay and energy efficient multi‐operand binary tree adder

Patel

Singhal

2020

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

Here, the critical path of ripple carry adder (RCA)-based binary tree adder (BTA) is analysed to find the possibilities for delay minimisation. Based on the findings of the analysis, the new logic formulation and the corresponding design of RCA are proposed for the BTA. The comparison result shows that the proposed RCA design offers better efficiency in terms of area, delay and energy than the existing RCA. Using this RCA design, the BTA structure is proposed. The synthesis result reveals that the proposed 32-operand BTA provides the saving of 22.5% in area-delay product and 28.7% in energy-delay product over the recent Wallace tree adder which is the best among available multi-operand adders. The authors have also applied the proposed BTA in the recent multiplier designs to evaluate its performance. The synthesis result shows that the performance of multiplier designs improved significantly due to the use of proposed BTA. Therefore, the proposed BTA design can be a better choice to develop the area, delay and energy efficient digital systems for signal and image processing applications.

show abstract

Section: Performance Analysis Of Proposed Bta In Multipliersmentioning

confidence: 99%

“…For this purpose, three recent multiplier structures, namely array multiplier [34], Wallace multiplier [34] and Booth multiplier [35] are analysed. Firstly, we have analysed

M \times N

false(N - 1 false)

number of addition stages to generate the final product.…”

Section: Performance Analysis Of Proposed Bta In Multipliersmentioning

confidence: 99%

“…Secondly, the

M \times N

Section: Performance Analysis Of Proposed Bta In Multipliersmentioning

confidence: 99%

Section: Performance Analysis Of Proposed Bta In Multipliersmentioning

confidence: 99%

See 2 more Smart Citations

Area–delay and energy efficient multi‐operand binary tree adder

Patel

Singhal

2020

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

show abstract

“…The partial products are then accumulated to generate the final result. The above steps can be performed using several algorithms [27][28][29][30][31]. Some of them are suitable to achieve high computational speed, while others are more suitable to save occupied resources.…”

Section: Motivations and Backgroundmentioning

confidence: 99%

Parallel architecture of power‐of‐two multipliers for FPGAs

Perri

Spagnolo

Frustaci

et al. 2020

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

This research work presents a novel approach to design efficient power-of-two multipliers on modern fieldprogrammable gate arrays (FPGA) devices. Several ways of exploiting fixed-point power-of-two multiplications have been recently demonstrated to reduce the computational complexity of several computationally intensive applications, such as computer vision, deep learning, and many others. Modern FPGA devices provide speed-optimised intellectual property (IP) cores based on embedded modules, such as digital signal processing blocks, and area-optimised IP cores based on reconfigurable logic resources, such as look-up tables and flip-flops. Unfortunately, due either to their limited available amount or to their limited running frequency, these IP cores do not allow the overall computational capability offered by an FPGA device to be completely exploited. While the speed-optimised version of the multiplier proposed here is fast enough to increase the number of operations performed per second by up to 4.3 times, with respect to the conventional designs, its area-optimised implementation reduces resources requirements and energy consumption by up to 22 and 40%.

show abstract

ASIC implementation of ECG denoising FIR filter by using hybrid Vedic–Wallace tree multiplier

Janwadkar,

Dhavse

2023

Circuit Theory & Apps

View full text Add to dashboard Cite

The design of hand‐held portable devices for cardiovascular health monitoring based on the analysis of electrocardiogram (ECG) is a hot topic of research nowadays. Digital filters, possibly designed using digital multipliers, are a critical module in the design of such analysis systems. This paper presents the ASIC design of a 64th‐order digital low‐pass FIR filter to be used in ECG denoising applications. The FIR filter is optimized for usage in battery‐operated portable systems, wherein power consumption and on‐chip area are crucial parameters of concern. These challenges are met by employing a novel multiplier architecture, which we design by hybridizing the two popular digital multiplication algorithms, namely, the Vedic multiplication algorithm and the Wallace tree multiplication algorithm. The proposed multiplier consumes lower area and power consumption than either of the aforementioned conventional multiplication algorithms. This is established through FPGA‐based implementations on Artix‐7 FPGA, for the various wordlengths. The area and power optimizations are further exercised by two proposed techniques, namely, elimination of redundant multipliers, and power gating using the proposed zero‐detector circuit. RTL‐to‐GDSII flow has been completed using Cadence digital design and sign‐off tools for SCL 180 nm technology. The results indicate that the proposed filter architecture occupies 16.38% lower area and 79.58% lower power consumption than the contemporary designs described in the literature.

show abstract

Comparative analysis of various types of multipliers for effective low power

Cited by 25 publications

References 20 publications

Area–delay and energy efficient multi‐operand binary tree adder

Area–delay and energy efficient multi‐operand binary tree adder

Parallel architecture of power‐of‐two multipliers for FPGAs

ASIC implementation of ECG denoising FIR filter by using hybrid Vedic–Wallace tree multiplier

Contact Info

Product

Resources

About