Comparative low frequency noise analysis of bipolar and MOS transistors using an advanced complementary BiCMOS technology

Babcock, J.A.; Loftin, B.; Madhani, Pankaj M.; Chen, Xinfen; Pinto, A.; Schroder, D.K.

doi:10.1109/cicc.2001.929806

Cited by 13 publications

(23 citation statements)

References 13 publications

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“…These exhibit lower noise corners and coefficients than their lateral pnp and MOS counterparts [8], [9] which are subject to the random trapping and de-trapping of carriers at the Si-SiO interface due to their surface current conduction [10]. Indeed, corners in excess of 1 MHz render many modern CMOS processes impractical.…”

Section: A Manufacturing Processmentioning

confidence: 99%

A TID and SEE Radiation-Hardened, Wideband, Low-Noise Amplifier

Mossawir

Linscott

Inan

et al. 2006

IEEE Trans. Nucl. Sci.

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We have developed a radiation-hardened, highly linear, wideband, low-noise amplifier (LNA) with programmable gain to serve as the front-end of a plasma-wave instrument for satellite-based electric-field measurements of very low frequency (VLF) phenomena in the Van Allen radiation belts. Fabricated in a commercial 0.25-m silicon-germanium BiCMOS process, this ASIC leverages radiation-hardness-by-design techniques at the topological, implementation, and layout levels to maintain 75-dB spurious-free dynamic range (SFDR) over nearly four decades of frequency, from 100 Hz to 1 MHz, for both proton and -ray total ionizing dose (TID) exposures up to 1000 krad(Si). Single-event effect (SEE) testing via pulsed laser confirms negligible latchup sensitivity and suppression of single-event transients(SETs) at the output for beam energy LET equivalents in excess of 100 MeV-cm 2 /mg in even the most sensitive regions of the die.

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Section: A Manufacturing Processmentioning

confidence: 99%

A TID and SEE Radiation-Hardened, Wideband, Low-Noise Amplifier

Mossawir

Linscott

Inan

et al. 2006

IEEE Trans. Nucl. Sci.

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“…• The increases of battery powered equipment strongly increase the demand for integrated circuits operating at a low supply voltage and with minimum power consumption [130,39,28]. This is also a reason for choosing SOI instead of bulk in the future, [20,42] since it is more suited to low voltage applications.…”

Section: Soi Advantagesmentioning

confidence: 99%

“…Standard LOCOS (Local Oxidation of Silicon) or STI (Shallow Trench Isolation) processes are employed to provide lateral isolation from adjacent devices. [130,129,78]Most of the early SOI devices were fabricated with SOS (Silicon-On-Sapphire) wafers. The unique feature of today's SOI wafers is that they have a buried silicon oxide (Buried Oxide, or BOX) layer extending across the entire wafer, just below a surface layer of device-quality singlecrystal silicon.. At the present time, most SOI wafers are fabricated by use of one of two basic approaches.…”

Section: Introductionmentioning

confidence: 99%

Silicon on Insulator Technology Review

Singh¹,

Saxena²,

Rastogi³

2011

IJESET

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“…This is because the MOSFET suffers from traps in the oxide, which leads to an increase in 1/f-noise. The bipolar transistors on the other hand are bulk conduction devices and have an order of magnitude lower 1/f-noise compared to the surface channel conduction of CMOS devices [4]. Recently, the authors compared the 1/fnoise performance of passive double-balanced mixers using diode-connected HBTs and Schottky diodes implemented in a SiGe BiCMOS technology.…”

Section: A Sige Bicmos Double-balanced Mixer Withmentioning

confidence: 99%