Comparative study of full adder circuit with 32nm MOSFET, DG-FinFET and CNTFET

Huq, S. M. Ishraqul; Nafreen, Maskura; Rahman, Tasnim; Bhadra, Sushovan

doi:10.1109/icaee.2017.8255323

Cited by 5 publications

(3 citation statements)

References 11 publications

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“…These effects encompass short channel phenomena, increased leakage current, drain induced barrier lowering, and concerns related to device reliability, all of which collectively compromise the overall performance of the device [13][14][15]. The limitations associated with attempting to scale down traditional semiconductor devices have led researchers to look into the following possible solutions [16][17][18]:…”

Section: Metal-oxide Semiconductor Field Effect Transistormentioning

confidence: 99%

MOSFET on the Horizon: What’s New and What’s Next

Dixit

2024

MOSFET - Developments and Trends

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This chapter mainly enlighten about the development and trends of the field effect transistors (FETs) in the nanoelectronics industries. According to Moore’s law, the number of transistors doubles in every 2 years because of transistor’s size is scaled down. Though the scaling of MOSFET has been the driving force towards the technological advancement, but due to continuous scaling various secondary effect which include; short channel effects, high leakage current, excessive process variation and reliability issue degrades the device performance. In today’s era, researchers are developing nano scaled transistors using various types of materials with different device geometries to reduce the limitations of conventional MOSFET. This chapter focuses on the development history, current-status and future trends of transistors. At the same time, the various protentional applications of nano-transistor discussed in this chapter.

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Section: Metal-oxide Semiconductor Field Effect Transistormentioning

confidence: 99%

MOSFET on the Horizon: What’s New and What’s Next

Dixit

2024

MOSFET - Developments and Trends

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“…The charge at the inception of the channel is almost autonomous of the drain voltage when the gate capacitance is greater than quantum. Semiconducting CNTs were used to fabricate CNTFETs that show promise over silicon based MOSFETs due to their superior electrical characteristics [6] [7].…”

Section: Carbon Nano Tube Field Effect Transistormentioning

confidence: 99%

“…Primarily, the MOSFET logic circuits are constructed based on a generic Process Design Kit using 32nm Predictive Technology Model (PTM) with 32nm as Physical Channel Length, 1.5nm as thickness of high-k top gate dielectric material (Tox) and 0.35eV as Fermi level of the doped S/D (Efo). Then, the CNTFET PTM circuit models as shown in Table 1 [6] that consist of device modelling implemented in HSPICE circuit simulator [7] are being compared to the MOSFET designs.…”

Section: Carbon Nano Tube Field Effect Transistormentioning

confidence: 99%

Performance Analysis of Montgomery Multiplier using 32nm CNTFET Technology

Mathan

Jayashri²,

Alias

et al. 2019

IJEEI

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VLSI design vacillating the parameters results in variation of critical factors like area, power and delay. The dominant sources of power dissipation in digital systems are the digital multipliers. A digital multiplier plays a major role in a mixture of arithmetic operations in digital signal processing applications hinge on add and shift algorithms. In order to accomplish high execution speed, parallel array multipliers are comprehensively put into application. The crucial drawback of these multipliers is that it exhausts more power than any other multiplier architectures. Montgomery Multiplication is the popularly used algorithm as it is the most efficient technique to perform arithmetic based calculations. A high-speed multiplier is greatly coveted for its extraordinary leverage. The primary blocks of a multiplier are basically comprised of adders. Thus, in order to attain a significant reduction in power consumption at the chip level the power utilization in adders can be decreased. To obtain desired results in performance parameters of the multiplier an efficient and dynamic adder is proposed and incorporated in the Montgomery multiplier. The Carbon Nanotube field effect transistor (CNTFET) is a promising new device that may supersede some of the fundamental limitations of a silicon based MOSFET. The architecture has been designed in 130nm and 32nm CMOS and CNTFET technology in Synopsys HSpice. The analysed parameters that are considered in determining the performance are power delay product, power and delay and comparison is made with both the technologies.The simulation results of this paper affirmed the CNTFET based Montgomery multiplier improved powerconsumption by 76.47%,speed by 72.67% and overall energy by 67.76% as compared to MOSFET-based Montgomery multiplier.

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Intelligent Signal Gating-Aware Energy-Efficient 8-Bit FinFET Arithmetic and Logic Unit

Ajitha¹,

Reddy

2021

Circuits Syst Signal Process

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Comparative study of full adder circuit with 32nm MOSFET, DG-FinFET and CNTFET

Cited by 5 publications

References 11 publications

MOSFET on the Horizon: What’s New and What’s Next

MOSFET on the Horizon: What’s New and What’s Next

Performance Analysis of Montgomery Multiplier using 32nm CNTFET Technology

Intelligent Signal Gating-Aware Energy-Efficient 8-Bit FinFET Arithmetic and Logic Unit

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