Comparative Study on the Performance of Five Different Hall Effect Devices

Abstract

Five different Hall Effect sensors were modeled and their performance evaluated using a three dimensional simulator. The physical structure of the implemented sensors reproduces a certain technological fabrication process. Hall voltage, absolute, current-related, voltage-related and power-related sensitivities were obtained for each sensor. The effect of artificial offset was also investigated for cross-like structures. The simulation procedure guides the designer in choosing the Hall cell optimum shape, dimensions and device polarization conditions that would allow the highest performance.

Research Update: Magnetoionic control of magnetization and anisotropy in layered oxide/metal heterostructures

“…For this geometry, the difference in geometry correction factor should be below 25%. 35 In the following, we neglect this contribution of the area outside the cell to the measured AHE signal. Thus, the electrochemically induced changes reported later on are underestimated by a small extent.…”

SOI Hall cells design selection using three-dimensional physical simulations

“…By referring to the previous papers of the first author, for Hall devices integrated in CMOS technology we can say that there is an important increase in the absolute sensitivity of the sensors. The Basic cell integrated in a bulk CMOS technology was tested and provided an absolute sensitivity S A ¼82 mV/T for V bias ¼2.3 V, (as presented in Figure 19 b) in paper [9]. The same device integrated in SOI technology provided S A ¼5 mV/T for V bias ¼0.1 V, as it can be seen in Fig.…”

“…We can observe that for Hall cells fabricated in the same process, the geometrical correction factor G which is a number between 0 and 1 is what makes the difference. Therefore, maximum sensitivity can be achieved through geometry optimization, as it was thoroughly investigated by the first author in previous papers [8][9][10][11][12].…”

“…Section 5 is summing up the simulation results and discusses them, by also making a comparison between the performance of the same Basic Hall cell studied in regular bulk and SOI CMOS technology respectively. Finally the paper concludes in Section 6. have been performed by the first author in various recent papers [8][9][10][11][12][13][14][15][16]. CMOS Hall cells offset and temperature drift were analyzed in details in [13].…”

“…The influence of the geometry on the Hall device performance is very important and was studied in [8][9][10]. Various designs for CMOS Hall devices were proposed and their behavior tested in [11][12].…”