SOI Hall cells design selection using three-dimensional physical simulations

Investigation into the capabilities of Hall cells integrated in a non-fully depleted SOI CMOS technological process

“…Three dimensional physical simulations of magnetic field influence on the semiconductors were previously performed by the author in [8,9], in order to assess the device performance.…”

“…An architecture based on SOI CMOS Hall effect sensor was used for high temperature applications [7]. SOI Hall cells behaviour was previously investigated by the author through three-dimensional physical models [8,9].…”

Optimization of structural and technological parameters of the field effect Hall sensor

“…A 400 nm buried oxide layer (2) was created by a known technique [4] on a silicon substrate (1) of n-type conductivity with a concentration of 5·10 16 cm -3 . The buried oxide separates a 200 nm device layer (3), also called an active area, from the bulk silicon.…”

“…It is important to note that the threshold sensitivity of SOI FEHS's exceeds by an order of magnitude that of silicon HS's [4]. The buried oxide reduces the substrate leakage currents by several orders of magnitude resulting in an increase in operating temperature in comparison with standard HS's (from -40 to 125 °C) [3].…”

“…When the ratio L / W = 2 the geometrical factor G equals 0.95, and when the ratio L / W = 3 the correction factor is only 1 %. Therefore, there is no point in increasing the length-to-width ratio and in practice it is usually in the range of 2 to 3 [4].…”