Comparing Synchronous, Mesochronous and Asynchronous NoCs for GALS Based MPSoCs

Ax, Johannes; Kucza, Nils; Vohrmann, Marten; Jungeblut, Thorsten; Porrmann, Mario; Rückert, Ulrich

doi:10.1109/mcsoc.2017.19

Cited by 12 publications

(8 citation statements)

References 21 publications

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“…When the network is running at full load, the energy consumption of the asynchronous circuit is similar to that of the synchronous circuit that improves the power supply, that is to say, it consumes more energy than the synchronous circuit with a normal power supply. Asynchronous network-on-chip is not suitable for MPSoC which needs to run at full capacity [25]. The power consumption of asynchronous circuits has a faster growth rate than that of synchronous circuits: using asynchronous networks to transmit data per unit length consumes more energy.…”

Section: Low Power Designmentioning

confidence: 99%

Design and Development of Low Power Clock and Data Recovery Circuit for Asynchronous Network on Chips

Nagalaxmi

Rao²,

P.Chandrasekar

2022

JICS

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Today, the current buffered router Synchronous Network on Chip architecture consumes significant chip area and power. Therefore, based on biased routing, buffer-less routers have recently been predicted as a possible solution, but they suffer from contiguous port assignments, slow critical paths, and increased latency. Asynchronous Network on Chip architecture emerges as the best option for avoiding glitches and consuming less power. A clock and data recovery circuit is used to recover the clock signal from the router-generated data and reduce power consumption in a Multiprocessor System on Chip. This paper proposes a clock and data recovery circuit design for an asynchronous Network on Chip. The proposed 4x4 Mesh router architecture implemented in this paper can process 64-bit of data samples with a depth of 64. When comparing the proposed architecture with the existing NoC architecture, the proposed architecture has shown a power reduction of 5times. The proposed architecture has consumed a total power of 0.103W.

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Section: Low Power Designmentioning

confidence: 99%

Design and Development of Low Power Clock and Data Recovery Circuit for Asynchronous Network on Chips

Nagalaxmi

Rao²,

P.Chandrasekar

2022

JICS

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“…Due to the asynchronous handshake protocol employed in the end-to-end communication, the NoC frequency does not limit the number of hops in a path, which makes the approach scalable. Our proposal also addresses the clock domain crossing drawback that still is a concern in the GALS paradigm [16] [17].…”

Section: Related Workmentioning

confidence: 99%

Reducing NoC Energy Consumption Exploring Asynchronous End-to-end GALS Communication

Weber

Oliveira

Carara

et al. 2020

2020 33rd Symposium on Integrated Circuits and Systems Design (SBCCI)

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Systems-on-Chip (SoCs) with a large number of cores adopt Networks-on-chip (NoCs) as the communication infrastructure due to its scalability. The complexity to distribute a skew-free synchronous clock signal over the entire chip increases in current fabrication technologies due to the process variability. Thus, designers may choose among fully asynchronous and Globally Asynchronous, Locally Synchronous (GALS) NoCs. This work proposes an intermediate solution. Each Intellectual Property (IP) core may have its clock domain, and the NoC supports both synchronous and asynchronous communication. The NoC has its own clock domain, with the synchronous communication used to establish end-to-end paths. Once the end-to-end path is established, the NoC connects the IPs asynchronously, as wires with repeaters. The message is transmitted using handshake protocol at the source IP frequency. The benefit of the proposal is the reduction in the communication energy consumption (up to 52%). The cost is a latency increase (16% to 30%) and area overhead (4%).

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“…However, the main advantage of GALS is its modular design, that is to say, each block may easily be replaced or reused according to the options available to the designer [4] [5]. In literature, two methods for communication in a GALS system may be commonly found, the first is the use of an asynchronous wrapper [6] [7] that envelops the block and employs handshake protocols to exchange data with other blocks, and the second is the use of a FIFO buffer for each communication channel [8] [9], each block communicates with the buffer as opposed to directly with one another, thus bypassing any synchronization issues. The latter method has become dominant over the former throughout the years.…”

Section: Related Work a Gals Systemsmentioning

confidence: 99%

Asynchronous Interfaces for IOPT-Flow to Support GALS Systems

Almeida

Moutinho

Campos-Rebelo

2019

IECON 2019 - 45th Annual Conference of the IEEE Industrial Electronics Society

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Throughout the course of time, distributing a global clock signal over a synchronous circuit has become a demanding task as a result of the broadening size and complexity of modern circuits. Globally Asynchronous Locally Synchronous (GALS) systems emerge as a solution to the laborious task of distributing a global clock over a large circuit, through the partitioning of said circuit into smaller, and therefore, more manageable blocks. The DS-Pnet (Dataflow, Signals and Petri nets) modelling language and its associated framework IOPT-Flow focus on supporting the development of cyber-physical systems, however, they may be a strong push to the development of GALS systems, through their multiple available tools that comprise a graphical editor, a simulator and automatic code generation tools, namely a VHDL (VHSIC Hardware Description Language) code generator. In order to facilitate the implementation of said GALS system in the IOPT-Flow framework, some components were created, these work together to form asynchronous interfaces that are a crucial element to any GALS system, thus providing options to designers that intent to develop a GALS system utilizing the IOPT-Flow framework.

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Comparing Synchronous, Mesochronous and Asynchronous NoCs for GALS Based MPSoCs

Cited by 12 publications

References 21 publications

Design and Development of Low Power Clock and Data Recovery Circuit for Asynchronous Network on Chips

Design and Development of Low Power Clock and Data Recovery Circuit for Asynchronous Network on Chips

Reducing NoC Energy Consumption Exploring Asynchronous End-to-end GALS Communication

Asynchronous Interfaces for IOPT-Flow to Support GALS Systems

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