Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec

Coz, Julien Le; Flatresse, Philippe; Engels, Sylvain; Valentian, Alexandre; Belleville, Marc; Raynaud, C.; Croain, Damien; Urard, Pascal

doi:10.1109/isscc.2011.5746343

Cited by 5 publications

(2 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The best tradeoff is based on the stacked devices, leading to the best retention leakage gain (50 to 70% reduction), for a small area overhead (6%) and no speed penalty, when compared to a similar floating body implementation. In addition to [1], this result paves the way toward PD-SOI circuits exhibiting a lower operating power for an equivalent stand-by power, than equivalent CMOS bulk circuits. …”

Section: Discussionmentioning

confidence: 77%

“…CMOS 65nm LP PD-SOI technology achieves, compared to Bulk, a 20% higher speed at same nominal Vdd. Whereas at same speed, by reducing PD-SOI Vdd supply, 30% of dynamic power consumption is saved [1]. This is obtained thanks to lower junction capacitances and Floating Body Effect (FBE) which decreases the transistors threshold voltages (Vt).…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

65nm PD-SOI glitch-free Retention Flip-Flop for MTCMOS power switch applications

Le-Coz

Flatresse

Clerc

et al. 2011

2011 IEEE International Conference on IC Design &Amp; Technology

View full text Add to dashboard Cite

This work presents a partially depleted Silicon-on-Insulator (PD-SOI) low-static power consumption Retention Flip-Flop (REFF). This flip-flop is designed in order to avoid wake-up transient glitches. In addition specific leakage reduction techniques are used to compensate the extra leakage currents induced by the SOI floating body effects. This leads to a static power consumption reduced by 2 for only 6% of extra silicon area, compared to a regular floating body implementation.

show abstract

Section: Discussionmentioning

confidence: 77%

Section: Introductionmentioning

confidence: 99%

65nm PD-SOI glitch-free Retention Flip-Flop for MTCMOS power switch applications

Le-Coz

Flatresse

Clerc

et al. 2011

2011 IEEE International Conference on IC Design &Amp; Technology

View full text Add to dashboard Cite

show abstract

A low jitter active body-biasing control-based output buffer in 65nm PD-SOI

Soussan

Majcherczak

Valentian

et al. 2011

2011 IEEE International Conference on IC Design &Amp; Technology

Self Cite

View full text Add to dashboard Cite

This paper proposes a specific low jitter and high speed Ouput interface which takes advantage of the Partially Depleted Silicon-on-Insulator technology while avoiding its drawbacks related to floating body effects. Thanks to an active body-biasing control technique, the additional jitter related to PD-SOI history effect, as well as the higher static leakage current compared to bulk technology, are more than compensated. In depth analyses are presented to highlight the robustness of this technique with respect to the other solutions considering various capacitive loads and temperatures.

show abstract

Dual-threshold-voltage configurable circuits with three-independent-gate silicon nanowire FETs

Zhang

Gaillardon

Micheli

2013

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)

View full text Add to dashboard Cite

Abstract-We extend ambipolar silicon nanowire transistors by using three independent gates and show an efficient approach to implement dual-threshold-voltage configurable circuits. Polarity and threshold voltage of uncommitted devices are determined by applying different bias patterns to the three gates. Uncommitted logic gates can thus be configured to implement different logic functions for dual-threshold-voltage design using a wiring scheme, to target either high-performance or low-leakage applications. Synthesis of benchmark circuits with these devices shows comparable performance and 54% reduction of leakage power consumption compared to FinFET technology.

show abstract

Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec

Cited by 5 publications

References 5 publications

65nm PD-SOI glitch-free Retention Flip-Flop for MTCMOS power switch applications

65nm PD-SOI glitch-free Retention Flip-Flop for MTCMOS power switch applications

A low jitter active body-biasing control-based output buffer in 65nm PD-SOI

Dual-threshold-voltage configurable circuits with three-independent-gate silicon nanowire FETs

Contact Info

Product

Resources

About