Comparison of Different Etching Techniques in Order to Reveal Dislocations in Thick Ge Layers

Abstract

For the first time, we have evidenced a real correlation between 3 techniques used for defect delineation on Ge layers. Possible and different mechanisms of preferential etching will be also discussed. In the present paper we studied, namely, Cr- free wet-etching solution, gas phase HCl etching and Secco solution. Using optical microscope in the Nomarski contrast and AFM, we have studied the dislocations density and etch pits shape as a function of the etched thicknesses. Datas were compared with plan view TEM. Values close to 1E07cm-2 have been obtained in both cases, confirming the ability of the Cr-free solution to reveal dislocations. Similar values have been obtained on such thick Leti Ge layers after some Secco etch. The EPD values found using Secco are in good agreement with the ones found after HCl and Cr-free etches.

A Review of Different and Promising Defect Etching Techniques: from Si to Ge

“…Some authors have noticed an influence of the strain field distribution on the HCl etch rate (28). The HCl etch pits have been found to be equivalent in terms of densities and distribution with the ones observed after (i) Schimmel on SiGe virtual substrates (27)(28), (ii) Secco on strained-silicon layers (27)(28)(29) and (iii) Secco and Crfree etches on pure epitaxial Ge (11). A lateral and anisotropic etching leading to the formation of inverted pyramids with different depths has been evidenced after HCl etches of Ge.…”

“…The nearly 1 µm thick constant composition SiGe layers sitting on top of our virtual substrates are nearly fully relaxed (macroscopic degrees of strain relaxation in-between 95% and 100%) and characterized by Threading Dislocations Densities around 10 5 cm -2 , typically. The Ge thick layers are in a slightly tensile strain configuration, with a TDD of the order of 10 7 cm -2 (11). Conventional SOI substrates samples obtained thanks to the Smart-Cut™ Technology were used for defect etching studies.…”

Epitaxial Growth of Ge Thick Layers on Nominal and 6oC off Si(001); Ge Surface Passivation by Si

“…A clear impact of the thermal cycling on the Threading Dislocations Densities (TDD) in 2.5 µm thick Ge layers was evidenced, with a reduction from 2x10 7 down to 7x10 6 cm -2 on nominal surfaces. Given that TDD quantification after HCl defect etching was difficult on 6° off surfaces, we have also used Secco wet etching, which is a quite powerful defect revelation technique (22). The same kind of TDD reduction upon annealing was then noticed on 2.5 µm Ge layers after removing roughly 1 µm of Ge : from 5x10 7 down to 10 7 cm -2 (same values for layers grown on nominal and 6° off Si(001) substrates).…”

“…The High Temperature ECS Transactions, 16 (10) 583-590 (2008) 10.1149/1.2986815 © The Electrochemical Society (HT : 600°C -850°C) used for the growth of the second, topmost, Ge layer lowers the dislocation density and reduces the overall deposition time. High temperature thermal cycling (in-between 750°C and 875°C-900°C, typically) can be called upon to further reduce the amount of defects in the layers (thanks to thermally assisted glide of the threading arms of misfit dislocations and mutual annihilation or elimination at wafer edges) (2), ( 17), (21)(22). Such a process is time-consuming, however.…”

Investigation of the Low Temperature / High Temperature Approach to Produce Si0.5Ge0.5 and Pure Ge Strain Relaxed Buffers

“…We have indeed plotted in the bottom part of Figure 5 the TDD evolution as a function of thickness in cyclically annealed Ge layers grown on 300mm Si wafers. Extrapolating to 2.5 µm of Ge would yield a TDD of 2.3x10 7 cm -2 , a value twice higher than with other defect counting techniques (20). This is partly due to the intrinsic width of XRD peaks in the qX direction which is not taken into account in the Ayers' formula (the Si substrate peak in Fig.…”