2019 International Conference on Electrical, Electronics and Computer Engineering (UPCON) 2019
DOI: 10.1109/upcon47278.2019.8980221
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Comparison of Linearity and Intermodulation Distortion Metrics for T - and Pi - Gate HEMT

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Cited by 8 publications
(4 citation statements)
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“…Where, f corresponds to the frequency of operation, f T is the cut off frequency of the device, I opt is the optimum drain current (in Amperes) for minimum noise operation, E c is the critical field (in MV/cm), R G and R S are the gate and source resistances (in Ω) respectively. Due to the increased fringing fields contributing to an increased parasitic capacitance in π -Gate [36][37][38], and due to the increased gate resistance as a courtesy of 40 nm spacer layer present between the 'π' architecture legs, the said architecture exhibits degraded NF min in comparison to the T -Gate counterpart. Further, the cut off frequency of the device depends upon the gate feedback capacitance (f T ≈ g m /2πC gg ) and therefore has a major effect on the NF min metrics.…”
Section: Resultsmentioning
confidence: 99%
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“…Where, f corresponds to the frequency of operation, f T is the cut off frequency of the device, I opt is the optimum drain current (in Amperes) for minimum noise operation, E c is the critical field (in MV/cm), R G and R S are the gate and source resistances (in Ω) respectively. Due to the increased fringing fields contributing to an increased parasitic capacitance in π -Gate [36][37][38], and due to the increased gate resistance as a courtesy of 40 nm spacer layer present between the 'π' architecture legs, the said architecture exhibits degraded NF min in comparison to the T -Gate counterpart. Further, the cut off frequency of the device depends upon the gate feedback capacitance (f T ≈ g m /2πC gg ) and therefore has a major effect on the NF min metrics.…”
Section: Resultsmentioning
confidence: 99%
“…The author further studies the RF performance of the said device architecture in an asymmetric modification under Class AB operation and concludes that the device demonstrates reliable operation against the hot electron effect with modest tradeoffs on the device performance. The study was further extended by Sehra et al [37][38] to investigate the device performance at higher frequency with regard to the device linearity and its response in presence of the unwanted harmonics that may distort the signal transfer. It was observed that the π -Gate architecture is capable in exhibiting a highly linear operation and shows suppressed response to intermodulation distortion which further suggests the suitability of the said architecture for low noise applications.…”
Section: Introductionmentioning
confidence: 99%
“…The group reports that the π-shaped gate modifies the electric field in the channel in the form of two steps that allow the electrons to thermalize and lose energy, thereby bringing down the overall temperature of the device. Sehra et al [25,26] extended the study to test the reliability, linearity, and intermodulation distortion metrics of the proposed device architecture.…”
Section: Introductionmentioning
confidence: 99%
“…A novel Π-gate architecture was presented by Alvaro et al, 14 which is proved to have a better thermal and reliable RF performance. Detailed analysis on the various prospects and optimization of Π-gate design was presented by Sehra et al [15][16][17] However, the greatest challenge in the device design and optimization is the convergence complexity and time requirements during simulation and parameter extraction when dealing with conventional TCAD tools.…”
mentioning
confidence: 99%