Comparison of low-temperature electrical characteristics of gate-all-around nanowire FETs, Fin FETs and fully-depleted SOI FETs

Tachi, Kazuyuki; Barraud, S.; Kakushima, Kuniyuki; Cristoloveanu, S.; Ernst, T.

doi:10.1016/j.microrel.2011.01.004

Cited by 5 publications

(6 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The nanosheet preparations are still based on the anisotropic etching of the Si x Ge y superlattice. The etching rate can be controlled by varying the composition and with different etching techniques [ 19 , 20 , 21 , 26 , 27 , 28 ]. Worth mentioning achievement is the seven-level nanosheet structure reported on a 150-nm-thick Si 0.7 Ge 0.3 /Si multilayers [ 28 ].…”

Section: Discussionmentioning

confidence: 99%

“…However, mobility optimization can also be achieved according to the channel structure if the channel length cannot be shortened. In the 3D FinFET and VNSFET, considering the mobility values are different in different crystal orientations and are size dependent, there are technical values to compare the effective mobility of FinFET and VNSFET [ 17 , 19 , 20 , 21 , 25 ].…”

Section: The Effect Of Channel Mobility On Scalingmentioning

confidence: 99%

“…It was reported that the nanosheet and nanowire transistor usually have smaller channel mobility than the conventional ones [ 19 , 20 , 21 , 25 ]. Additionally, the mobilities are also found to be size-dependent.…”

Section: Effect Of Mobility Nanosheet and Fin Sizingmentioning

confidence: 99%

“…The surface region to bulk silicon ratio in a FinFET is smaller. It was reported that the mobility of FinFET is 2.5 times larger than the nanowire with the same width [ 21 ].…”

Section: Effect Of Mobility Nanosheet and Fin Sizingmentioning

confidence: 99%

“…Fin width, fin height, and intersheet spacing are the key limiting factors. On the other hand, a nanosheet should have a smaller cross-section and a larger surface region, which is found to cause significant mobility degradation [ 17 , 19 , 20 , 21 ]. Meanwhile, it was reported that the 3 nm fab constructed by TSMC will still be based on FinFET technology.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

On the Vertically Stacked Gate-All-Around Nanosheet and Nanowire Transistor Scaling beyond the 5 nm Technology Node

Wong

Kakushima

2022

Nanomaterials

Self Cite

View full text Add to dashboard Cite

This work performs a detailed comparison of the channel width folding effectiveness of the FinFET, vertically stacked nanosheet transistor (VNSFET), and vertically stacked nanowire transistor (VNWFET) under the constraints of the same vertical (fin) height and layout footprint size (fin width) defined by the same lithography and dry etching capabilities of a foundry. The results show that the nanosheet structure has advantages only when the intersheet spacing or vertical sheet pitch is less than the sheet width. Additionally, for the nanowire transistors, the wire spacing should be less than 57% of the wire diameter in order to have a folding ratio better than a FinFET with the same total height and footprint. Considering the technological constraints for the gate oxide and metal gate thicknesses, the minimum intersheet/interwire spacing should be in the range of 7 to 8 nm. Then, the VNSFET structure has the advantage of boosting the chip density over the FinFET ones only when the sheet width is wider than 8 nm. On the other hand, the VNWFET structure may have a better footprint sizing than the FinFET ones only when the nanowire diameter is larger than 14 nm. In addition, considering the different channel mobilities along the different surface directions of the silicon channel and also some other unfavorable natures such as more complicated processes, more significant surface roughness scattering, and parasitic capacitance effects, the nanosheet transistor does not show superior scaling capability than the FinFET counterpart when approaching the ultimate technology node.

show abstract

Section: Discussionmentioning

confidence: 99%

Section: The Effect Of Channel Mobility On Scalingmentioning

confidence: 99%

Section: Effect Of Mobility Nanosheet and Fin Sizingmentioning

confidence: 99%

“…The surface region to bulk silicon ratio in a FinFET is smaller. It was reported that the mobility of FinFET is 2.5 times larger than the nanowire with the same width [ 21 ].…”

Section: Effect Of Mobility Nanosheet and Fin Sizingmentioning

confidence: 99%