Comparison of the Reliability of Thin $\hbox{Al}_{2} \hbox{O}_{3}$ Gate Dielectrics Prepared by In Situ Oxidation of Sputtered Aluminum in Oxygen Ambient With and Without Nitric Acid Compensation

Abstract

The electrical characteristics and reliability of the aluminum oxide (Al 2 O 3 ) metal-oxide-semiconductor (MOS) capacitors were investigated under low-temperature process consideration. The simple cost-effective technique in preparing the Al 2 O 3 /SiO 2 bilayer structure as the high-k gate dielectrics was demonstrated in this paper. SiO 2 was prepared by roomtemperature anodic oxidation, and Al 2 O 3 was fabricated by room-temperature in situ natural oxidation during the dc sputtering of aluminum in Ar/O 2 ambient. Compared to the Al 2 O 3 MOS capacitors without nitric acid (HNO 3 ) compensation, significant improvements in electrical characteristics, reliability, and uniformity were achieved by utilizing HNO 3 to moderately oxidize the existing Al 2 O 3 layer. In addition, the charge trapping behaviors of our samples were also studied by time-dependent dielectric breakdown under the 1000-s constant voltage stress and constant current stress tests. It was found that the electron trapping is dominant under a low negative bias stress. However, under a high negative bias stress, the Al 2 O 3 MOS capacitors show hole trapping due to the impact ionization near the SiO 2 /Si interface. The in situ oxidation in sputtering with HNO 3 compensation is suitable for future low-temperature dielectric applications.Index Terms-Al 2 O 3 , anodic oxide, HNO 3 compensation, low temperature, metal-oxide-semiconductor (MOS) capacitor.

Effect of Electrons Trapping/De-Trapping at Si-SiO2Interface on Two-State Current in MOS(p) Structure with Ultra-Thin SiO2by Anodization

“…Electron trapping in the dielectric layer or at the interface traps after CVS is well delineated in the literature. 11,12,18 Figure 3 is the plot of negative stressing voltage of negative CVS versus flatband voltage (V FB ) after consecutive negative CVS. The insets show the plots of capacitance-voltage (C-V) curves after consecutive negative CVS.…”

“…[6][7][8] Thus, considerable methods have been brought up to solve these problems. [9][10][11][12][13] Current-voltage (I-V) measurements have been widely adopted to investigate the electrical characteristics of MOS devices. Comprehensive mechanisms of gate current tunneling through a dielectric layer are notable, such as direct tunneling (DT), Fowler-Nordheim tunneling (FNT), and trap assisted tunneling (TAT).…”

Electrical Characteristics and Temperature Response of Al2O3 Gate Dielectrics with and without Nitric Acid Compensation

“…5(b). Therefore, J E can be expressed as J ∝ J ୰ + J ୣ୶ [5] where J rg is the generation-recombination current in the depletion region (18), and J ex is the extra current components come from oxide nonuniformity and interface trap density at higher substrate temperature. It is noted that the generation-recombination current in the depletion region is…”

Investigation of nonuniformity phenomenon in nanoscale SiO2 and high-k gate dielectrics

“…After the same RTA process, ultrathin hafnium films were deposited with various thicknesses at room temperature in the sputter system. The room temperature nitric acid oxidation (NAO) technique [15][16][17][18] was implemented to form HfO 2 layer. The samples were immersed in HNO 3 with a concentration of HNO 3 :H 2 O ¼ 1:1 for 10 min.…”