Comparison of Two Internal Miller Compensation Techniques for LDO Regulators

A low power consumption and fast response low voltage difference linear regulator circuit is designed for on-chip SOC circuit to achieve low power consumption, fast response, and high stability. The internal design mainly includes a low power bandgap reference circuit, a light and heavy load detection circuit, and a transient enhancement circuit. The circuit is designed with 0.35 μm BCD technology, and the layout design is completed. The VIN is from 2.5 V to 5 V, the VOUT from 2.5 V to 3.3 V, and the maximum load is 250 mA. The simulation results show that the static current is 2.6 μA at normal temperature with no load. When the load jumps, the overshoot is 44 mV and the recovery time is 52 μs, meeting the design requirements of low power consumption and fast response.

Section: Low Power Consumption Fast Response Ldomentioning

confidence: 99%

Low power consumption and fast response of low dropout regulator design

Wei,

Huang,

Wang

2024

“…The Miller capacitor C1 pushes the secondary pole to a frequency point greater than the unit-gain bandwidth, and the zeroing resistor R1 pushes the zero far beyond the secondary pole so that it does not affect the gain attenuation rate. In this design, the low-frequency gain is expected to be 80 dB and the phase margin is to be 63° [5] . Figure 4 shows the design structure of the adjusting tube, which provides two guarantees for the stability of LDO.…”

Section: Bandgap Reference Circuitmentioning

confidence: 99%

An LDO without a Capacitor Required in Applications

Shi,

Fan,

Huang

2023

Linear voltage regulator with low voltage dropout is widely used in DC/DC circuits because of the advantages of simple structure, low noise, high efficiency, and small package size. In this paper, high stability LDO linear voltage regulator with low static current is designed. By using a voltage detection module, the pass transistor in the regulator can be quickly regulated or switched on and off under load transient conditions. In addition, the stability of the LDO is improved by using an NMOS pass transistor and diode clamp architecture. The test results show that the typical values of linear adjustment and load adjustment of the voltage regulator are 20 mV and 200 mV, respectively. The maximum output current is 60 mA, the load current is 20 mA, and the output pressure difference under 4.8 V output voltage is 210 mV. Compared with traditional LDO, although the output current is not the maximum, the difference and stability of output pressure are greatly improved.

“…The main pole is designed to be located at the output node of the error amplifier. For the stability of the system, a compensation capacitor C M is added [6] .…”

Section: Ldo Circuit Designmentioning

confidence: 99%

A Fast Transient Low-Dropout Regulator with High-Power Supply Rejection

Bai

Guo

Yang

et al. 2022

With the continuous popularization of portable electronic products in electronic information, aerospace, biomedicine and other fields, low-dropout regulator (LDO) has become an important part of modern power management chips. Compared with other power management modules, it has the advantages of low power consumption, high power supply rejection, and strong anti-noise capability. However, the LDO power tube has a large width-to-length ratio, so when the load changes transiently, the gate of the power tube cannot respond in time, resulting in an overshoot and undershoot of the output voltage and a long recovery time. In this paper, the LDO transient enhancement circuit is designed. When the load changes transiently, the power tube gate capacitor is quickly charged and discharged, which overcomes the overshoot voltage and undershoot voltage. While improving the transient response of traditional LDO, the structure ensures the power supply rejection (PSR) and other performance of the circuit. According to the results, with an input of 2.5 V, the output voltage is regulated to 1.2 V, and PSR is -80 dB. When the load changes by 20 mA in 1 μs, it is stable within 1.2 μs while the undershoot voltage is controlled at 51 mV and the overshoot voltage is controlled at 65 mV.