With the rapid development of social economy, the integrated circuit industry has developed rapidly. At the same time, people’s requirements for the cost, power consumption, integration, stability and other aspects of integrated circuit chips have increased. Oscillators, as an important module for providing clocks to chips, have higher requirements for on-chip oscillators. The purpose of this paper is to achieve a low supply voltage sensitive and low power oscillator. Based on this research purpose, this paper proposes a power adjustment oscillator circuit of the flip level technique, which realizes that the clock signal duty cycle is 50% under the typical case of a supply voltage of 4 V. The center frequency is 512 KHz, of which the process angle trimming range of the capacitor trim circuit is 52.37%-211.28%. With the supply voltage range of 2.5 V to 5.5 V, the clock signal has a frequency variation of 0.299%/V, has low supply voltage sensitivity, and consumes only 400 nA with low power dissipation.

With the continuous popularization of portable electronic products in electronic information, aerospace, biomedicine and other fields, low-dropout regulator (LDO) has become an important part of modern power management chips. Compared with other power management modules, it has the advantages of low power consumption, high power supply rejection, and strong anti-noise capability. However, the LDO power tube has a large width-to-length ratio, so when the load changes transiently, the gate of the power tube cannot respond in time, resulting in an overshoot and undershoot of the output voltage and a long recovery time. In this paper, the LDO transient enhancement circuit is designed. When the load changes transiently, the power tube gate capacitor is quickly charged and discharged, which overcomes the overshoot voltage and undershoot voltage. While improving the transient response of traditional LDO, the structure ensures the power supply rejection (PSR) and other performance of the circuit. According to the results, with an input of 2.5 V, the output voltage is regulated to 1.2 V, and PSR is -80 dB. When the load changes by 20 mA in 1 μs, it is stable within 1.2 μs while the undershoot voltage is controlled at 51 mV and the overshoot voltage is controlled at 65 mV.