Compensating for Quantizer Delay in Excess of One Clock Cycle in Continuous-Time $\Delta\Sigma$ Modulators

Singh, Vikas; Krishnapura, Nagendra; Pavan, Shanthi

doi:10.1109/tcsii.2010.2058496

Cited by 21 publications

(55 citation statements)

References 9 publications

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“…2 [5]. The fourth integrator is used to integrate with R 4 C 4 and opamp and the same opamp is used to sum feedforward voltages with a 0 C 4 , a 1 C 4 , a 2 C 4 and, a 3 C 4 along with C 4 .…”

Section: System Level Designsmentioning

confidence: 99%

Analytical method to determine optimal out-of-band gain in multi-bit delta-sigma modulator

Anand

Koirala

Pokharel

et al. 2012

IEICE Electron. Express

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A simple, systematic and deterministic MATLAB simulation which employs Risbo method and analytical simulation is proposed to determine the optimal out-of-band gain to achieve a maximal SNR and the maximum stable amplitude in a multi-bit delta-sigma modulator. Using the proposed method, a 128 MS/s, 2 MHz signal bandwidth 4 th order 2-bit continuous-time delta-sigma modulator is designed and implemented in 0.18 µm CMOS technology to verify the concept. As a result, the modulator achieves a peak SNDR of 79.3 dB and a dynamic range of 83 dB for a 2 MHz signal bandwidth (OSR = 32) while consuming only 7.8 mW from 1.8 V supply.

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Section: System Level Designsmentioning

confidence: 99%

Analytical method to determine optimal out-of-band gain in multi-bit delta-sigma modulator

Anand

Koirala

Pokharel

et al. 2012

IEICE Electron. Express

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“…This way, most literature on the stability of multi-bit sigma delta modulation focused on the robustness against parasitic effects [10]- [13]. However in practice, any quantizer has only a limited input (and output) range.…”

Section: Introductionmentioning

confidence: 99%

A Describing Function Study of Saturated Quantization and Its Application to the Stability Analysis of Multi-Bit Sigma Delta Modulators

Rombouts

Bock

Maeyer

et al. 2013

IEEE Trans. Circuits Syst. I

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Abstract-Just as their single-bit counterparts, multi-bit sigma delta modulators exhibit nonlinear behavior due to the presence of the quantizer in the loop. In the multi-bit case this is caused by the fact that any quantizer has a limited output range and hence gives an implicit saturation effect. Due to this, any multi-bit modulator is prone to modulator overloading. Unfortunately, until now, designers had to rely on extensive timedomain simulations to predict the overloading level, because there is no adequate analytical theory to model this effect.In this work, we have developed such an analytical theory based on multiple input describing function analysis. This way, we obtained expressions for the signal gain, the noise gain and the variance of the quantization noise. Here, both the case of DC as well as sinusoidal signals was considered. These results were used for the stability analysis of multi-bit Sigma Delta modulators, which allows to predict the overloading level. Code implementing the proposed expressions is available for download at

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“…Several CT-△Σ modulator achieving 10-12 bits resolution with a signal bandwidth ranging from [5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20] MHz have been recently reported [1]. Another technique which has been recently explored is to increase the quantizer sampling rate, in a given technology node, by absorbing excess loop-delay (ELD) greater than one clock cycle in the loop [2], [3]. We introduced the first 500MS/s, 25MHz BW CT-△Σ ADC which employed a two-step quantizer with 5-bit resolution [4].…”

Section: Introductionmentioning

confidence: 99%

“…CT-△Σ MODULATOR WITH ELD > T s Fig. 1 shows the modified CT-△Σ modulator block diagram, incorporating an ELD compensation technique of more than one clock cycle [2]. Here, the ELD compensation is achieved 860 978-1-4799-0066-4/13/$31.00 ©2013 IEEE …”

Section: Introductionmentioning

confidence: 99%

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Systematic synthesis of cascaded continuous-time ΔΣ ADCs for wideband data conversion

Balagopal

Zhu

Saxena

2013

2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)

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Continuous-time delta sigma (CT-∆Σ ) ADCs are gaining wider adoption in data conversion systems primarily aided by their robustness to mismatch in nano-scale CMOS technologies and inherent anti-alias filtering. In past, several techniques have been employed to achieve wider conversion bandwidths by either scaling the designs to a lower technology node or by adopting architectures with lower oversampling ratios (OSR). Cascaded, or MASH, CT-∆Σ ADCs have been explored to achieve conversion bandwidths by cascading lower order ∆Σ loops followed by a digital coarse quantization noise canceling filter (NCF). Another technique which has recently been explored is to increase the quantizer sampling rate, in a given technology node, by absorbing excess loop-delay (ELD) greater than one clock cycle (Ts) in the loop. However, these techniques individually cannot sufficiently meet the ever increasing bandwidth demand for the broadband wireless applications. Further, the ELD > Ts designs require an extra modulator order to achieve the same noise-shaping performance as the lowspeed ELD < 0.5 Ts prototype, necessitating high-order CT-∆Σ loops. As a step towards combing the two techniques, we propose a systematic design method to synthesize 3-2 MASH CT-∆Σ modulators to achieve higher conversion bandwidths, BW ≥ 40M Hz in a 130-nm CMOS technology.

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Compensating for Quantizer Delay in Excess of One Clock Cycle in Continuous-Time $\Delta\Sigma$ Modulators

Cited by 21 publications

References 9 publications

Analytical method to determine optimal out-of-band gain in multi-bit delta-sigma modulator

Analytical method to determine optimal out-of-band gain in multi-bit delta-sigma modulator

A Describing Function Study of Saturated Quantization and Its Application to the Stability Analysis of Multi-Bit Sigma Delta Modulators

Systematic synthesis of cascaded continuous-time ΔΣ ADCs for wideband data conversion

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Compensating for Quantizer Delay in Excess of One Clock Cycle in Continuous-Time $\Delta\Sigma$ Modulators

Cited by 21 publications

References 9 publications

Analytical method to determine optimal out-of-band gain in multi-bit delta-sigma modulator

Analytical method to determine optimal out-of-band gain in multi-bit delta-sigma modulator

A Describing Function Study of Saturated Quantization and Its Application to the Stability Analysis of Multi-Bit Sigma Delta Modulators

Systematic synthesis of cascaded continuous-time &#x0394;&#x03A3; ADCs for wideband data conversion

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Systematic synthesis of cascaded continuous-time ΔΣ ADCs for wideband data conversion