Compiled simulation of programmable DSP architectures

Zivojnovic, V.; Tijang, S.; Meyr, H.

doi:10.1109/vlsisp.1995.527490

Cited by 37 publications

(34 citation statements)

References 6 publications

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“…The PALF register allocation scheme was implemented on ORC infrastructure, and the performance was evaluated on the PAC DSP with a cycle-accurate instruction set simulator [18], by running the DSPstone benchmark suite [19]. We first inspected the proposed PALF scheme and validated the effect of several phases.…”

Section: Experiments and Discussionmentioning

confidence: 99%

PALF: compiler supports for irregular register files in clustered VLIW DSP processors

Lin

You

Lee

2007

Concurrency and Computation

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SUMMARYWide varieties of register file architectures -developed for embedded processorshave turned to aim at reducing the power dissipation and die size these years, by contrast with the traditional unified register file structures. This article presents a novel register allocation scheme for a clustered VLIW DSP, which is designed with distinctively banked register files in which port access is highly restricted. Whilst the organization of the register files is designed to decrease the power consumption by using fewer port connections, the cluster-based design makes register access across clusters an additional issue, and the switched-access nature of the register file demands further investigations into optimizing register assignment for increasing the instruction-level parallelism. We propose a heuristic algorithm, named ping-pong aware local favorable (PALF) register allocation, to obtain advantageous register allocation that is expected to better utilize irregular register file architectures. The results of experiments performed using a compiler based on the Open Research Compiler (ORC), showed significant performance improvement over the original ORC's approach, which is considered to be an optimized approach for common register file architectures.key words: register allocation; ping-pong register file; DSP; VLIW

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Section: Experiments and Discussionmentioning

confidence: 99%

PALF: compiler supports for irregular register files in clustered VLIW DSP processors

Lin

You

Lee

2007

Concurrency and Computation

View full text Add to dashboard Cite

show abstract

“…In combination, we have been able to simulate the benchmarks only 1.1-2.5 times slower than the execution of their counterparts directly compiled on the host machine, when tracing is off. This result is on average 2 times faster than the state of the art [4] [3] [6].…”

Section: Introductionmentioning

confidence: 90%

“…The simulator [2] reports a 25 times slow down of the native execution. [6] reported that it takes DSP simulators provided by vendors 6.4 hours to simulate G.726 speech transcoder for 13 seconds of speech signals, in contrasts to the 7 seconds of native execution time.…”

Section: Interpretation Based Simulationmentioning

confidence: 99%

“…In [6], Such simulators are developed for DSP processors. The authors reported 200-640 times speed up than the corresponding interpretative simulator.…”

Section: Related Workmentioning

confidence: 99%

“…The host can emit C code (e.g., C Host in Figure 3), an approach equivalent to [6]; or directly emit host machine assembly (e.g., Sparc Host in Figure 3). …”

Section: Simulation Code Generation Interfacementioning

confidence: 99%

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