Completion Detection-Based Timing Error Detection and Correction in a Near-Threshold RISC-V Microprocessor in FDSOI 28 nm

Uytterhoeven, Roel; Dehaene, Wim

doi:10.1109/lssc.2020.3006626

Cited by 10 publications

(11 citation statements)

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“…no margins and operation at or beyond PoFF). To accomplish this, the EDaC technique first proposed in [17] looks at the completion of logic operations in the datapath at the end of the clock period to determine instantaneously the presence of late arriving signals. This is in contrast with DS monitoring techniques that make a longer observation during the DW and thus require additional hold constraints.…”

Section: Presented Instantaneous Error Detectionmentioning

confidence: 99%

“…1) Clock gating: Similar to [18] and [17], a clock cycle is skipped using a clock gate at the root of the clock-tree triggered by the error flag. This provides an additional clock period for the late signals to settle and guarantees that the timing error is resolved.…”

Section: Error Correctionmentioning

confidence: 99%

“…The implementation of this improved EDaC technique targets an ultra low power DSP processor. This is a significantly larger system compared to small microprocessor in [17] and shows that the technique scales to larger designs. Furthermore, this new implementation allows a more in depth analysis of the effective energy gains obtained by using the EDaC system and investigates the relation between these savings and different signoff corners.…”

Section: Introductionmentioning

confidence: 99%

“…To that end, it combines the advantages of prediction based EDaC systems and detection based systems into a new EDaC concept. This concept has first been proposed in [17] and is here explained in more detail. Further, this work offers several improvements to the original technique including a significant reduction in the area footprint of the individual monitors, a pruning of redundant monitoring elements, and a new low impact clock stretching correction method.…”

Section: Introductionmentioning

confidence: 99%

“…Furthermore, this new implementation allows a more in depth analysis of the effective energy gains obtained by using the EDaC system and investigates the relation between these savings and different signoff corners. Additionally, the effect on the processors throughput is analyzed and compared for both the original correction method in [17] and the new correction method added in this work.…”

Section: Introductionmentioning

confidence: 99%

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Design Margin Reduction Through Completion Detection in a 28-nm Near-Threshold DSP Processor

Uytterhoeven

Dehaene

2022

IEEE J. Solid-State Circuits

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This paper presents a timing error detection and correction (EDaC) technique optimized for near/sub-threshold operation to recover energy lost in the conventional signoff margins. The presented EDaC requires no modifications to the processor pipeline and avoids imposing additional holdconstraints on monitored paths by instantaneously checking for late activity. Further, two correction methods are discussed, a simple clock gating method and a low cycle overhead clock stretching method. Both provide robust last-minute error prevention. The EDaC is applied in a near/sub-threshold implementation of the CoolFlux DSP processor and infers only a 2.8 % and 2.1 % area overhead for the detection and correction respectively. Silicon measurements validate the EDaC system from 0.25 V to 0.7 V (1 MHz to 200 MHz) and show that it recovers all voltage margins in the near/sub-threshold region. The design achieves a MEP of 8.1 pJ/cycle at 0.34 V and 10 MHz. Here, the EDaC technique reduces the energy consumption by 48 % to 17.6 % with respect to the signoff margins depending on their conservatism, and it enables the processor to operate with only 12 % energy overhead compared to its ideal non-margined critical operation point.

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Section: Presented Instantaneous Error Detectionmentioning

confidence: 99%

Section: Error Correctionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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