Complex 3D CMOS circuits based on a triple-decker cell

Roos, Gerhard; Hoefflinger, B.

doi:10.1109/4.142603

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Cited by 13 publications

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“…Some results have appeared in the literature discussing three-dimensional (3-D) circuits and architectures: some focus on the creation of 3-D logic gates and building blocks, while others examine the possibility of creating more complex circuits and architectures [7][8][9][10][11][12].…”

Section: Introductionmentioning

confidence: 99%

Three dimensional system on chip technology

Swartzlander

2005

Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)

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With ever-finer device geometry, increasing device counts and interconnect delays playing a larger role in the performance of a system on a chip, the architectures that are used to support such technologies must take these factors into account. Highly pipelined or highly parallel architectures that utilize local processing, and therefore shorter interconnects, are required.Three-dimensional, monolithic integrated circuit technology which can significantly shorten the interconnects and accommodate more devices per chip may be an attractive solution. The basic idea is presented along with an illustrative application specific processor design.

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