Complexity-effective multicore coherence

Abstract

Much of the complexity and overhead (directory, state bits, invalidations) of a typical directory coherence implementation stems from the effort to make it "invisible" even to the strongest memory consistency model. In this paper, we show that a much simpler, directory-less/broadcast-less, multicore coherence can outperform a directory protocol but without its complexity and overhead. Motivated by recent efforts to simplify coherence, we propose a hardware approach that does not require any application guidance. The cornerstone of our approach is a dynamic, application-transparent, write-policy (write-back for private data, write-through for shared data), simplifying the protocol to just two stable states. Self-invalidation of the shared data at synchronization points allows us to remove the directory (and invalidations) completely, with just a data-race-free guarantee from software. This leads to our main result: a virtually costless coherence that outperforms a MESI directory protocol (by 4.8%) while at the same time reducing shared cache and network energy consumption (by 14.2%) for 15 parallel benchmarks, on 16 cores.

A Dual-Consistency Cache Coherence Protocol

“…SC-for-DRF protocols rely on the guarantee that, during DRF regions, threads perform either private or read-only memory accesses [1], [2], [20]. A memory access is private if it targets a memory location that is only accessed by one thread during the execution of one DRF region; and is read-only if the location is not written within the DRF region.…”

“…This excessive invalidation limits their performance [1], [2]. In contrast, SPEL reduces self-invalidation, by relying on the compiler to indicate the points of synchronization that indeed require self-invalidating cached data.…”

“…While previous proposals classified memory accesses for guiding data placement [7], [13] or optimizing coherence protocols (e.g., reducing self-invalidation [2], reducing directory pressure [11], [21]), SPEL relies on the delineation of xDRF regions to minimize the coherence maintenance while providing SC guarantees, for any code. Next we review the most widely adopted approaches for memory access classification.…”

“…However, not only traditional protocols perform sub-optimally on modern architectures, but their inefficiency escalates as the number of cores in the system grows. State of the art coherence protocols seek to detect and exploit memory accessing characteristics of code with the goal of simplifying the protocol while delivering scalability and performance [1], [2]. Despite the promising results, such protocols exhibit limitations (for instance, fail at providing support for legacy code), and were therefore disregarded for being integrated in the emerging architectures (e.g., Intel Xeon Phi [3]), which still implement traditional, inefficient, directory-based cache coherence protocols.…”

“…However, it comes at the cost of performance limitations, especially when the system provides a more relaxed consistency model [4]. In answer, modern coherence protocols follow the sequential consistency for data-race-free (SC for DRF) model [5], which allows a simpler and more scalable design [1], [2] and improves performance [6]. Nevertheless, a major drawback is that such protocols do not provide backwards compatibility with existing software that requires a stronger consistency model.…”