Engineers who design hard real-time embedded systems express a need for several times the performance available today while keeping safety as major criterion. A breakthrough in performance is expected by parallelizing hard real-time applications and running them on an embedded multi-core processor, which enables combining the requirements for high-performance with timing-predictable execution.parMERASA will provide a timing analyzable system of parallel hard real-time applications running on a scalable multicore processor. parMERASA goes one step beyond mixed criticality demands: It targets future complex control algorithms by parallelizing hard real-time programs to run on predictable multi-/many-core processors. We aim to achieve a breakthrough in techniques for parallelization of industrial hard real-time programs, provide hard real-time support in system software, WCET analysis and verification tools for multi-cores, and techniques for predictable multi-core designs with up to 64 cores.

The EC project parMERASA (Multicore Execution of Parallelized Hard Real-Time Applications Supporting Analyzability) investigated timing-analyzable parallel hard real-time applications running on a predictable multicore processor. A pattern-supported parallelization approach was developed to ease sequential to parallel program transformation based on parallel design patterns that are timing analyzable. The parallelization approach was applied to parallelize the following industrial hard real-time programs: 3D path planning and stereo navigation algorithms (Honeywell International s.r.o.), control algorithm for a dynamic compaction machine (BAUER Maschinen GmbH), and a diesel engine management system (DENSO AUTOMOTIVE Deutschland GmbH). This article focuses on the parallelization approach, experiences during parallelization with the applications, and quantitative results reached by simulation, by static WCET analysis with the OTAWA tool, and by measurement-based WCET analysis with the RapiTime tool.

In multicore systems, the concurrent access to shared data generates a bottleneck for the system performance. Cache coherence techniques have been introduced to enable fast access while preserving the data coherence, but these coherence protocols are critical in hard real-time systems. Because the frequent inter-cache communication leads to unpredictable interferences between the cores, the system's timing behaviour is hard to analyse. In this paper, we propose a new, hard real-time capable strategy for multicore systems called on-demand coherent cache ODC 2 . The technique is based on marginal hardware extensions compared with noncoherent caches and the use of common synchronisation techniques. ODC 2 provides coherent accesses to cached shared data as well as caching of private data. Because the presented strategy does not induce interferences between local caches, ODC 2 is capable for hard real-time systems. We present an evaluation of performance and scalability of ODC 2 compared with two standard coherence protocols using a bus-based multicore system.

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