Extended performance analysis of the time predictable on-demand coherent data cache for multi- and many-core systems

Pyka, Arthur; Rohde, Mathias; Uhrig, Sascha

doi:10.1109/samos.2014.6893201

Cited by 8 publications

(6 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Software approaches for cache coherence require changing the application to handle the different copies of shared data explicitly. For instance, [55] modified the application to protect accesses to shared data by using lock mechanisms such that only one core at any time has access to the shared data. In the worst-case, this approach performs as well as the sequential execution of tasks sharing data.…”

Section: Software Solutionsmentioning

confidence: 99%

Dynamic Memory Bandwidth Allocation for Real-Time GPU-Based SoC Platforms

Aghilinasab

Ali

Yun

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

show abstract

Section: Software Solutionsmentioning

confidence: 99%

Dynamic Memory Bandwidth Allocation for Real-Time GPU-Based SoC Platforms

Aghilinasab

Ali

Yun

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

show abstract

“…main memory, are slow and may increase the WCET. On-Demand Coherent Cache [30] converts tasks accessing shared data to critical sections, hence disallowing concurrent execution of any tasks that share data. SWEL [31] focuses on high performance computing and message passing workloads.…”

Section: Related Workmentioning

confidence: 99%

Cache Where you Want! Reconciling Predictability and Coherent Caching

Bansal,

Singh,

Hao

et al. 2019

Preprint

View full text Add to dashboard Cite

Real-time and cyber-physical systems need to interact with and respond to their physical environment in a predictable time. While multicore platforms provide incredible computational power and throughput, they also introduce new sources of unpredictability. Large fluctuations in latency to access data shared between multiple cores is an important contributor to the overall execution-time variability. In addition to the temporal unpredictability introduced by caching, parallel applications with data shared across multiple cores also pay additional latency overheads due to data coherence. Analyzing the impact of data coherence on the worst-case execution-time of real-time applications is challenging because only scarce implementation details are revealed by manufacturers. This paper presents application level control for caching data at different levels of the cache hierarchy. The rationale is that by caching data only in shared cache it is possible to bypass private caches. The access latency to data present in caches becomes independent of its coherence state. We discuss the existing architectural support as well as the required hardware and OS modifications to support the proposed cacheability control. We evaluate the system on an architectural simulator. We show that the worst case execution time for a single memory write request is reduced by 52%.

show abstract

“…2) Since private data does not cause any coherence interference, uncacheshared allows caching of only private data, while uncaching of all shared data. In Figure 8, uncache-shared has better performance than uncache-all for all applications with a geometric mean slowdown of 2.11× Nonetheless, uncache-shared requires additional hardware and software modifications to distinguish and track cache lines with shared data, which are the same modifications required by [10]. 3) Mapping applications with shared data to the same core avoids data incoherence since these tasks share the same private cache.…”

Section: Exp2: Comparing Performance With Conventional Protocols mentioning

confidence: 99%

“…However, this solution requires special hardware performance counters and modifications to currently available scheduling techniques. A third solution suggests modifying the applications by marking instructions with shared data as critical sections such that they are accessed by only a single core at any time instance [10]. Although this allows caching of shared data, it stalls all tasks but one from accessing the data, which in worst case (WC) amounts to sequentially running the tasks.…”

Section: Introductionmentioning

confidence: 99%

“…For example, the solution in [9] is not adequate for partitioned scheduling mechanisms. A different solution introduced in [10] applied source-code modifications to mark instructions with shared data as critical sections. These critical sections were protected by locking mechanisms such that they were accessed only by a single core at any time instance.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Predictable Cache Coherence for Multi-core Real-Time Systems

Hassan

Kaushik

Patel

2017

2017 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)

View full text Add to dashboard Cite

Abstract-This work addresses the challenge of allowing simultaneous and predictable accesses to shared data on multi-core systems. We accomplish this by proposing a predictable cache coherence protocol, which mandates the use of certain invariants to ensure predictability. In particular, we enforce these invariants by augmenting the classic modify-share-invalid (MSI) protocol with transient coherence states, and minimal architectural changes. This allows us to derive worst-case latency bounds on predictable MSI (PMSI) protocol. Our analysis shows that while the arbitration latency scales linearly, the coherence latency scales quadratically with the number of cores. We implement PMSI in gem5, and execute SPLASH-2 and synthetic multi-threaded workloads. Our empirical results show that our approach is always within the analytical worst-case latency bounds, and that PMSI improves average-case performance by up to 4× over the next best predictable alternative. PMSI has average slowdowns of 1.45× and 1.46× compared to conventional MSI and MESI protocols, respectively.

show abstract

Extended performance analysis of the time predictable on-demand coherent data cache for multi- and many-core systems

Cited by 8 publications

References 19 publications

Dynamic Memory Bandwidth Allocation for Real-Time GPU-Based SoC Platforms

Dynamic Memory Bandwidth Allocation for Real-Time GPU-Based SoC Platforms

Cache Where you Want! Reconciling Predictability and Coherent Caching

Predictable Cache Coherence for Multi-core Real-Time Systems

Contact Info

Product

Resources

About