Comprehensive design guidance for PTH via stub in board-level high speed differential interconnects

Shin, Jaemin; Michalka, Timothy

doi:10.1109/ectc.2010.5490695

Cited by 12 publications

(3 citation statements)

References 2 publications

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“…3(a). Similar behavior has been observed on previous works having only via-stubs [6], [7]. Same figure shows that the resonance frequency point for each case decreases while increasing the routing stub length.…”

Section: Via and Routing Stub Impactsupporting

confidence: 87%

Signal integrity design of via with extra routing stub for device routing flexibility

Miralrio¹,

Ruiz²,

Lin³

et al. 2013

2013 IEEE Electrical Design of Advanced Packaging Systems Symposium (EDAPS)

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Computer systems today show a trend toward higher data rate, smaller form factor and flexible routing option to accommodate different configurations. This paper presents signal integrity impact study of having a routing stub on via in order to have a choice of which device to use. Via with routing stub is modeled using 3-D field solver. Signal integrity analysis is performed for PCIE Gen3 (8Gbps) and SATA3 (6Gbps) to demonstrate the margin loss due to various routing stub lengths. For the simulated topology, results show that for routing stub longer than 100mils, there is significant margin loss, which may even result in no solution space for PCIE Gen3 and SATA3. For routing stub less than 50mils, there is a few inches of solution space reduction equivalently according to the data rate.

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Section: Via and Routing Stub Impactsupporting

confidence: 87%

Signal integrity design of via with extra routing stub for device routing flexibility

Miralrio¹,

Ruiz²,

Lin³

et al. 2013

2013 IEEE Electrical Design of Advanced Packaging Systems Symposium (EDAPS)

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“…The insertion of stitching VIAs can be used to improve the performance in terms of modal conversion and insertion loss once the structure of the differential couple has been optimized [12,15,16]. The cited papers evidence the need for asymmetrical VIA organization, as any asymmetry increases the modal-conversion contributions [16,17]. In particular, Chen et al [15] showed how symmetrical structures should be used in association with the optimization of ground VIA positions by demonstrating that correct positioning can provide better results when compared to random placement of more ground VIAs.…”

Section: Introduction and State-of-the Artmentioning

confidence: 99%

“…This means that the signal components at any possible stub resonance frequency are strongly attenuated [7]. Shin et al [17] showed that, given the layer stack-up, no possible differential VIA variation affects such attenuation, but the stack-up itself strongly dominates it through the ground VIA. A resonance shift to higher frequencies is obtained when all of the ground layers in the stack-up are used.…”

Section: Introduction and State-of-the Artmentioning

confidence: 99%

An Optimization Framework for the Design of High-Speed PCB VIAs

et al. 2022

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Signal integrity represents a key issue in all modern electronic systems, which are strongly dominated by the extreme component density usually employed on PCBs and the associated increase in the interconnection density. The use of multi-layer structures with microstrips connected by various types of Vertical Interconnect Accesses (VIAs) calls for design strategies that reduce the impedance mismatch and signal attenuation. The paper proposes a thorough analysis of the effects associated with the VIA geometry and presents a parametric evaluation of them. The obtained results represent the starting point for a possible design procedure that manages the geometric aspects of differential VIAs, aiming to optimize their electrical performance while reducing their occupation of PCB area. The optimization technique considers a differential VIA as a four-port circuit whose characteristics are evaluated with suitable Figures of Merit (FoMs), thus striving for an optimal design obtained with closed-loop iterations. The analysis is performed in both the time (TDR: Time-Domain Reflectometry) and frequency domains (S and Z parameters), thus allowing a dramatic reduction in the number of cases to be analyzed. The procedure is thoroughly described and validated using simulation results.

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