The mathematical foundation of common integrated circuit yield models based on the assumption that the yield is dominated by random point defects is discussed. Various mathematical models which are commonly used to account for defect clustering are given a physical interpretation and are compared mathematically and graphically. A yield model applicable when the repair of some defects in a chip is possible is developed and discussed. Simple yield models for systems with two fold block redundancy and triple modular redundancy in the presence of defect clustering are developed and the implications for overall system yield are discussed. It is shown that the yield of systems with circuit redundancy can be substantially affected by defect clustering and hence that a correct understanding of defects and yield is essential to predict the yields and costs of wafer scale products.

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