Computer-Aided Design and VLSI Device Development

Cham, Kit Man; Oh, Soo‐Young; Moll, J.L.; Lee, Keunmyung; Voorde, Paul Vande; Chin, Daeje

doi:10.1007/978-1-4613-1695-4

Cited by 13 publications

(7 citation statements)

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“…It calls verified 2-D FCAP2 and 3-D FCAP3 [5][6J, which is based on the finite-difference method to generate accurate capacitance database in batch mode. It then provides a fast graphical user interface to display capacitance design curves.…”

Section: Interconneci Parameter Eracflonmentioning

confidence: 99%

“…In order to analyze and predict these degradation accurately, it has been widely observed that 2-D and 3-D simulations are necessary, especially for an accurate capacitance calculation in the submicron interconnect system[3J[4J [5][6] [7]. Several dosed-form equations were derived or approximated from measured data for fast capacitance calculations[8}[91, but their application to general submicron interconnects is rather limited, especially in the coupling capacitances.…”

Section: Introductionmentioning

confidence: 99%

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<title>Technological limitations in submicron on-chip interconnect</title>

Chang

et al. 1993

SPIE Proceedings

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The trend of the performance degradafions, noise and reliability issues and their potential solutions are analyzed for the submicron ULSI interconnect lines. To analyze these submicron interconnect lines, a new paradigm(HIVE) for fast and accurate 2-D and 3-D interconnect capacitances and resistances calculation is developed. The analysis, using these interconnect parameters from HIVE, shows that a copper(Cu) line will improve the elewomigrations, but not the interconnect delay and cross-talk noise significantly. The low temperature operation improve the interconnect delay and electromigralion, but it increases the cost of system packaging. The optimum approach will be the combination of additional layers of non-scaled metal lines in a higher level, low permittivity interlevel dielectri; and the use of repeaters to maximize the performance, noise and reliability and to minimize the risk and cost.

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Section: Interconneci Parameter Eracflonmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

<title>Technological limitations in submicron on-chip interconnect</title>

Chang

et al. 1993

SPIE Proceedings

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“…Among the many new non-volatile memories, PCM is considered to be one of the next generation of mainstream non-volatile memories due to its advantages such as high read speed, high write speed, long life, stable storage, simple process, and multi-level storage. In order to improve the yield of the chip, circuit simulation needs to be performed on the chip before the actual chip manufacturing, and device models are essential for circuit simulation [4]- [6].…”

Section: Introductionmentioning

confidence: 99%

A SPICE Model of Phase Change Memory for Neuromorphic Circuits

Chen

Huang

et al. 2020

IEEE Access

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A phase change memory (PCM) model suitable for neuromorphic circuit simulations is developed. A crystallization ratio module is used to track the memory state in the SET process, and an active region radius module is developed to track the continuously varying amorphous region in the RESET process. To converge the simulations with bi-stable memory states, a predictive filament module is proposed using a previous state in iterations of nonlinear circuit matrix under a voltage-driven mode. Both DC and transient analysis are successfully converged in circuits with voltage sources. The spiking-time-dependent-plasticity (STDP) characteristics essential for synaptic PCM are successfully reproduced with SPICE simulations verifying the model's promising applications in neuromorphic circuit designs. Further on, the developed PCM model is applied to propose a neuron circuit topology with lateral inhibitions which is more bionic and capable of distinguishing fuzzy memories. Finally, unsupervised learning of handwritten digits on neuromorphic circuits is simulated to verify the integrity of models in a large-scale-integration circuits. For the first time in literature an emerging memory model is developed and applied successfully in neuromorphic circuit designs, and the model is applicable to flexible designs of neuron circuits for further performance improvements.INDEX TERMS Neuromorphic circuits, phase change memory, SPICE model, spike-time-dependent plasticity, spiking neural networks.

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“…(3) In a submicron MOSFET, the depletion widths of the some and drain can be comparable in magnitude to the channel length, therefore critical device parameters such as the punchthrough voltage are sensitive to the actual doping profiles used [3]. The doping profiles used in a submicron MOSFET cannot be modeled accurately by simple analytical functions (Gaussian, erfc, etc.)…”

Section: Introductionmentioning

confidence: 99%

Single-event-induced charge collection and direct channel conduction in submicron MOSFETs

Velacheri

Massengill

Kerns

1994

IEEE Trans. Nucl. Sci.

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The singleevent (SE) charge collection of an n-channel submicron MOSFET is described using three dimensional device simulations. Ion hits in the drain and in the channel region are considered. For submicron MOSFETs, we show simulation evidence that there may exist a direct source-drain conduction process induced by the ion, called ion-triggered channeling (ITC), which may be an important SE upset mechanism in deep submicron scaling. The further study of of the MOSFET, which is typically the sensitive node. This quantity of charge is used as an indicative measure of a probable failure. Apart from describing this charge collection process, the aim of this study is also to highlight any charge enhancement process unique to submicron FETs. In particular, we have used a 3 4 Bolman transport code to study such a unique process, which we believe may be a dominant factor in the upset vulnerability of deep submicron CMOS. SIMULATION METHODOLOGYIn this work, a three-dimensional carrier transport code, [21 , has been used to model the single event hit at the device level. Using a 3-d simulator provides increased ion-track-length to device-gate-length ratios indicate that the direct source-drain conduction process assumes increased importance for increased scaling.

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Computer-Aided Design and VLSI Device Development

Cited by 13 publications

References 0 publications

<title>Technological limitations in submicron on-chip interconnect</title>

<title>Technological limitations in submicron on-chip interconnect</title>

A SPICE Model of Phase Change Memory for Neuromorphic Circuits

Single-event-induced charge collection and direct channel conduction in submicron MOSFETs

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