Concurrency-oriented verification and coverage of system-level designs

Abstract

Correct concurrent System-on-Chips (SoCs) are very hard to design and reason about. In this work, we develop an automated framework complete with concurrency-oriented verification and coverage techniques for system-level designs. Our techniques are different from traditional simulation-based reliability techniques, since concurrency information is often lost in traditional techniques. We preserve concurrency information to obtain unique verification techniques that allow us to predict potential errors (formulated as transactionlevel assertions) from error-free simulations. In order to do this, we exploit the inherent concurrency in the designs to generate and analyze novel partial-order simulation traces. Additionally, to evaluate the confidence on verification results and the gauge progress of verification, we develop novel mutation testing based on concurrent coverage metrics. Mutation testing is a fault insertion-based simulation technique that has been successfully applied in software testing. We present a comprehensive list of mutation operators for SystemC, similar to behavioral fault models, and show the effectiveness of these operators by relating them to actual bug patterns. We have successfully applied our verification and coverage techniques on industrial systems and demonstrated that current verification test suites need to be improved for concurrent designs, and we have found errors in systems that were tested previously.

A static analysis approach to data race detection in SystemC designs

“…So these methods can detect only errors that appear in the execution trace. To cope with this problem, a method which takes into account various schedulings is suggested in [4]. This method analyses all possible traces, based on the given execution trace.…”

Verification and coverage of message passing multicore applications

“…An example PRV tool, named BTV, is shown in Ogale and Garg [2007]. Our approach is similar to the work in Sen [2011] where predictive assertion verification and mutation testing have been applied to SystemC designs, which are used for hardware/software codesign. By contrast, our article targets message passing multicore applications and specifically applications written using the MCAPI standard.…”

“…By contrast, our article targets message passing multicore applications and specifically applications written using the MCAPI standard. In this work, we present predictive deadlock and race condition detection algorithms that do not exist in Sen [2011]. We have also developed a new mutation library for message passing applications.…”

Model-Based Virtual Prototype Acceleration

“…Model checking for SystemC (see [21]- [24]) shares the same challenge. But our solution is quite different from the cited approaches.…”

“…Searching is done in two phases: 1) forward traversal: breadth-first search of reachable states until the goal state s g is encountered in the employing lane (lines 6-10), and 2) backward traversal: determine a trace that reaches s g from s 0 by back stepping (lines [13][14][15][16][17][18][19][20][21][22][23][24][25]. In phase one, the not employing lane is stored in state sets S i , and the employing lane is represented by state setsŜ i .…”